1. Introduction to MOS Transistors

2. Outline
Similarity Between BJT & MOS
Introductory Device Physics

3. BJT & MOS Transistor

4. Regions of Operation Comparison
NMOS
PMOS

5. Regions of Operation

6. Introductory Device Physics

7. A Crude Metal Oxide Semiconductor (MOS) Device
V2 causes movement
of negative charges,
thus current.
V1 can control the
resistivity of the channel.
Positive charge attract
negative charges
to the interface between
insulator and silicon.
A conductive path is created
If the density of electrons is
sufficiently high.
Q=CV.
P-Type Silicon is
slightly conductive.
The gate
draws no current!

8. NMOS in 3D (provide electrons) (drain electrons) W n+ diffusion allows
electrons move
through silicon.

9. Typical Dimensions of MOSFETs
These diode must
be reversed biased.
tox is made really thin
to increase C, therefore,
create a strong control of Q by V.

10. A Closer Look at the Channel Formulation
Need to tie substrate to GND
to avoid current through PN
diode.
VTH=300mV to 500 mV
(OFF)
(ON)
Positive charges repel the holes
creating a depletion region, a region free of holes.
Free electrons appear at VG=VTH.

11. Change Drain Voltage
Resistance is determined by VG.

12. Change Gate Voltage
A higher VG leads to a lower channel resistance, therefore a larger slope.

13. Length Dependence fixed VD fixed VG
The resistance of a conductor is proportional to the length.

14. Dependence on Oxide Thickness
fixed VD
fixed VG
Q=CV
C is inversely proportional to 1/tox.
Lower Q implies higher channel resistance.

15. Width Dependence
The resistance of a conductor is inversely proportional to the cross
section area.
A larger device also has a larger capacitance!

16. Channel Pinch Off
Q=CV
V=VG-VOXIDE-Silicon
VOXIDE-Silicon can change along the channel! Low VOXIDE-Silicon implies less Q.

17. VG-VD is sufficiently large
to produce a channel
VG-VD is NOT sufficiently large
to produce a channel
No channel
Electrons
are swept
by E to drain.
Drain can no longer affect the drain current!

18. Regions
(No Dependence on VDS)
No channel
Assumption:

19. PMOS Transistors

20. PMOS in Cut-Off Mode P+ P+ N+ N P
Substrate= 0V

21. PMOS: Formation of Channel P+ P+ N+ N P
Substrate= 0V
Induced holes

22. PMOS in Triode Region P+ P+ N+ N P Substrate= 0V Induced holes P+ P+ N+ N P
Substrate= 0V
Induced holes

23. PMOS in Saturation Region P+ P+ N+ N P
Substrate= 0V
Induced holes

24. Compare NMOS Equation to PMOS Equation
(Cut-off)
(triode)
(saturation)
Valid for NMOS
(saturation)
(triode)
(Cut-off)
Valid for PMOS