1. Temperature Aware Circuits A Temperature Sensor in the Interconnect Layer Matthew Lindsey

2. Outline Background Modeling the Interconnect –Technology Nodes –Optimal Sizes Temperature Sensor Circuit Conclusions

3. Background Current interconnect design falls short –Self-heating and electromigration both temperature dependent No current technique to measure temperature in the interconnect Mostly based on Banerjee’s work

4. The Interconnect Distributed model –Physical parameters from ITRS –Circuit parameters from PTM Optimal size (length and buffer size) –Performance Planning by Otten and Brayton

5. Optimal Size Node: 90nm Lcrit (um) SoptRout (Ohms) Rline (Ohms) M188.2566.4490.88141.01 intermed98.1366.5881.85126.99 global156.5681.5644.8469.58

6. Self Consistent Equation From Banerjee r: duty cycle ton/T Tm: new metal temperature

7. 70nm: Global Interconnect Layer

8. The Sensor Modified ring oscillator circuit

9. Comparison 100C to 500C 90nm, global interconnect layer, using 150um length of wire

10. Conclusions Simulations Performed –130nm, 90nm, 70nm, for metal 1, intermediate and global interconnect for 100C to 500C in steps of 50C Found Temperature Sensor will be Effective in those Simulations Time Constraints Prevented Interconnect Model and Circuit Together in Same Simulation

11. Questions