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© imec 2004 1 Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and.

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Presentation on theme: "© imec 2004 1 Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and."— Presentation transcript:

1 © imec Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and Karen Maex* IMEC, Leuven, Belgium * Also at Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Belgium SLIP’2004, Paris February,2004

2 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris2 Introduction Backend Technology N + 1 Metal Dielectric Silicon N N : Tech. Node  More Functions per area  Less Cost per function

3 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris3 Interconnect Delay W. Wu, R. Jonckheere, M. Stucchi, H. Struyf, Z. Tőkei, I. Vervoort, I. Vos, F. Iacopi, and K. Maex, Studies on Resistivity of Narrow Cu Interconnects, Proceedings of Advanced Metallization Conference, pp , (San Diego, October 2002) Optical E-beam ITRS RC trends in ITRS 2003

4 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris4 Technology Issues S’~10nm! ‘Electrical equivalent sidewall damage’ F. Iacopi, M. Stucchi, O. Richard and K. Maex, ”Electrical Equivalent Sidewall Damage in Patterned Low-k Dielectrics”,to appear in Electrochemical and Solid-State Letters, 2004.

5 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris5 Interconnect Exploration Metal Dielectric Silicon NNNN Let us assume that scaling continues in spite of DSM issues NN Hard to improve material properties Window of freedom exists for interconnect exploration Power Delay Width and Height exploration for constant pitch

6 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris6 Interconnect Width Sizing  Width Sizing [ Lee2000,Alpert2001,Cong2002,Jiang2001 ]  Decreasing the wire width progressively from source to sink.(TWS)  Multiple Width Sizing (MWS or TWS)  Uniform Width Sizing (UWS) Driver Load Wire widthWire position Driver Load Driver Load Problems with routing

7 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris7 Interconnect Width Selection by Table Lookup Method Driver Interconnect 2 n 1 SlewInverterRN AdderC Buffer Mux. Length Type of load

8 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris8 4-D Lookup Table Variable slew Driver Variable C2 R Variable C1 C2C1 Variable R R = 0.48Rint C1 = 1/6Cint C2 = 5/6Cint + C L O’Brien/Savarino pi Model Pre- Characterized Delay and Power Table R C1 C2 slew Delay Power

9 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris9 Exploration Methodology (Case Study-1)

10 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris10 Circuit Example (2 pin net) Assumptions  Exploration for 45 nm node  Length information obtained by using rent’s rule for a simple isotropic model of an IC (a priori length information)  Analysis done for average wire length in 2 nd layer (440 um)  Driver and load both are 4x inverters  45nm BSIM4 model card used [1]  One width per layer assumed  T A  B and Total power dissipation were calculated Driver Interconnect Load A B [1] 4x 100 psec T10.5p T20.4p T30.3p T40.2p T50.1p width

11 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris11 Exploration of width for optimizing delay T10.5p T20.4p T30.3p T40.2p T50.1p

12 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris12 SI Analysis Vt T10.5p T20.4p T30.3p T40.2p T50.1p

13 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris13 Power vs. Delay Normalized w.r.t. T1 T10.5p T20.4p T30.3p T40.2p T50.1p

14 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris14 Including Buffer Sizing Normalized w.r.t. T1 and 4x Driver Interconnect Load A B 4x100 psec T10.5p T20.4p T30.3p T40.2p T50.1p 4x 1x 2x 4x 8x

15 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris15 Power-Delay Trade off’s Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

16 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris16 Local Interconnects ( length = 40 um) Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

17 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris17 Global Interconnects (length = 800 um) Normalized w.r.t. T1 and 4x T10.5p T20.4p T30.3p T40.2p T50.1p

18 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris18 Conclusions  Exploration can be done for interconnect dimensions  Informed choice for interconnect dimensions  Local Interconnects (very short wires…)  Not much Trade off is possible by width-only exploration  Smallest width is the best solution for constant pitch in context of power and delay optimization  Intermediate Interconnects  Significant Trade off can be made between delay and power  Global Wires  Dissipation can be traded for reducing the delay  Simultaneous buffer sizing and wire sizing is the best option  Future work  Variable pitch and height exploration  Better Signal Integrity evaluation models  Effect on area

19 © imec 2004 Mandeep Bamal, IMEC/ SLIP’2004, Paris19 Thank you! questions


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