1. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Final Project – UART & Multi Processing Fall, 2010 MPC8360 Micro Controllers 371-1-2403

2. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Universal Asynchronous Receiver/Transmitter (UART) ► UART takes a byte of data and transmits the individual bits in a sequential fashion ► At the destination, the UART re-assembles the bits into complete bytes Station A Tx Rx Station B Rx Tx

3. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. URBR(UART) Offset 0x4500 07 RWRW ResetAll Zeros DATA Data received from the transmitter on the UART bus [read only]

4. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. UTHR(UART) Offset 0x4500 07 RWRW ResetAll Zeros DATA Data that is written to UTHR [Write only]

5. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. UIER1(UART1) ERDAI Enable Received Data Available Interrupt 0 Mask interrupt when new receive data is available or receive data time-out has occurred. 1 Enable and assert interrupts when a new data character is received from the external device and/or a time-out interrupt occurs in FIFO mode. Offset 0x4501 07 RWRW … ERDAI ResetAll Zeros

6. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. ULCR1(UART1) DLAB Divisor latch access bit 0 Access to all registers except UDLB, UAFR, and UDMB. 1 Ability to access UDMB, UDLB, and UAFR. Offset 0x4503 07 RWRW DLAB WLS ResetAll Zeros

7. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. UTHR(UART) Offset 0x4500 07 RWRW ResetAll Zeros UDLB Divisor least significant byte. This is concatenated with UDMB.

8. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. UTHR(UART) Offset 0x4501 07 RWRW ResetAll Zeros UDMB Divisor Most significant byte. This is concatenated with UDMB.

9. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Universal Asynchronous Receiver/Transmitter (UART) Before configuring UDMB and UDLB ULCR[DLAB] must be asserted (`1`). After configuring UDMB and UDLB ULCR[DLAB] must be negated(`0`). ► The Division factor (UDMB | UDLB) should be 0x06c8. Tx Rx Tx

10. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. ULCR1(UART1) WLS Word Length Select Word length select. Number of bits that comprise the character length. 00 5 bits 01 6 bits 10 7 bits 11 8 bits Offset 0x4503 06,7 RWRW … WLS ResetAll Zeros

11. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. ULSR1(UART1) DR Data Ready 0 Cleared when URBR is read or when all of the data in the receiver FIFO is read. 1 A character was received in the URBR or the receiver FIFO. Offset 0x4505 07 RWRW … DR ResetAll Zeros

12. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Offset 0x4505 0 2 7 RWRW … THRE ResetAll Zeros ULSR1(UART1) THRE Transmitter Holding Register Empty 0 UTHR is not empty. 1 A data character has transferred from the UTHR into the internal transmitter shift register.

13. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Offset 0x4505 07 RWRW … BI ResetAll Zeros ULSR1(UART1) BI Break Interrupt 0 Cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received). 1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time. A new character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected. In FIFO mode, a zero character is encountered in the FIFO (the zero character is at the top of the FIFO). In FIFO mode, only one zero character is stored.

14. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. UART Programming Flow ► Update the programmable interrupt controller (PIC) DUART channel interrupt. ► Set data attributes and control bits in the ULCR. ► Set the interrupt enable register (UIER). ► To start a write transfer, write to the UTHR. ► Use Interrupts to receive data.

15. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Universal Asynchronous Receiver/Transmitter (UART) Station A Tx Rx Station B Rx Tx

16. TM Freescale Confidential Proprietary Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Quick Overview