2UART Universal Asynchronous Receiver/Transmitter Receive: Convert serial to parallel (SIPO)Transmit: Convert parallel to serial (PISO)Asynchronous: No clock; bytes sent in chunks.Start (0) and stop (1) signal for each byte
3EUSARTEnhanced Universal Synchronous / Asynchronous Receiver/TransmitterSynchronous: Constant stream of data matched with clock signal.More efficient, no start/stop framing required.Enhanced: Advanced featuresSleep mode/auto-wakeCalculate incoming baud rateError DetectionFull-duplex asynchronous, Half-duplex synchronous8 or 9 bit character length
4Flip-Flop Flip-flops store a single bit of data. SR NOR latch: Simplest type of flip flop.
5D Flip-FlopSimilar function, but uses clock to feed Data signal to Q in time with clock cycle.
6Receive Shift Register (RSR): Cascade of flip-flops Data written serially by shifting.Upon filling register, all bits read simultaneously on clock cycle.
7Transmit Altered shift register (TSR) reverses process. All bits written to register simultaneously.Bits shift to next flip-flop on cycles.Last bit feeds output.
8Registers TXSTA & RCSTA: Status registers. TSR & RSR: Shift registers. Set modes.TSR & RSR: Shift registers.Not directly accessible.TXREG & RCREG: Container for transmitted data.BAUDCTL: 8-bit Baud Rate Control Register.SPBRG & SPBRGH: 16-bit Baud Rate Generator.
9TXSTA – Transmit Status Register CSRC - Clock Source Select bit - determines clock source. It is used only in synchronous mode.1 - Master mode. Clock is generated internally from Baud Rate Generator0 - Slave mode. Clock is generated from external source.+TX9 - 9-bit Transmit Enable bit1 - 9-bit data transmission via EUSART system0 - 8-bit data transmission via EUSART system.*TXEN - Transmit Enable bit*1 - Transmission enabled0 - Transmission disabled.*SYNC - EUSART Mode Select bit1 - EUSART operates in synchronous mode0 - EUSART operates in asynchronous mode.SENDB - Send Break Character bit is only used in asynchronous mode and only in case it is required to observe LIN bus standard.1 - Sending Break character is enabled0 - Break character transmission is completed.*BRGH - High Baud Rate Select bit determines baud rate in asynchronous mode. It does not affect EUSART in synchronous mode.1 - EUSART operates at high speed0 - EUSART operates at low speed.TRMT - Transmit Shift Register Status bit1 - TSR register is empty0 - TSR register is full.TX9D - Ninth bit of Transmit Data can be used as address or parity bit.
10RCSTA – Receive Status Register *SPEN - Serial Port Enable bit*1 - Serial port enabled. RX/DT and TX/CK pins are automatically configured as input and output respectively0 - Serial port disabled.+RX9 - 9-bit Receive Enable bit1 - Receiving 9-bit data via EUSART system0 - Receiving 8-bit data via EUSART system.SREN - Single Receive Enable bit is used only in synchronous mode when the microcontroller operates as master.1 - Single receive enabled0 - Single receive disable.*CREN - Continuous Receive Enable bit acts differently depending on EUSART mode.Asynchronous mode:*1 - Receiver enabled0 - Receiver disabled.Synchronous mode:*1 - Enables continuous receive until the CREN bit is cleared0 - Disables continuous receive.+ADDEN - Address Detect Enable bit is only used in address detect mode.1 - Enables address detection on 9-bit data receive0 - Disables address detection. The ninth bit can be used as parity bit.~FERR - Framing Error bit1 - On receive, Framing Error is detected0 - No framing error.~OERR - Overrun Error bit.1 - On receive, Overrun Error is detected0 - No overrun error.RX9D - Ninth bit of Received Data can be used as address or parity bit.
11BAUDCTL – Baud Rate Control Register *Bit 7: ABDOVF — Flag bit indicates time of overflow; sets rate.1 - Auto-baud timer overflowed0 - Auto-baud timer did not overflow.Bit 6: RCIDL — Idle/Sleep; only used in asynchronous mode.1 - Receiver is idle0 - START bit has been received and receiving is in progress.Bit 4: SCKPSynchronous: indicate which Idle state is used for the data Clock (CK)1 - Synchronization on rising edge of the clock0 - Synchronization on falling edge of the clock.Asynchronous: indicate transmit polarity.1 - Transmit inverted data to the RC6/TX/CK pin0 - Transmit non-inverted data to the same pin.*Bit 3: BRG16 — Enable 16-bit1 – Enable 16-bit (disables BAUDCTL from setting rate).0 – Disable 16-bit mode.Bit 1: WUE — Auto-wake/Interrupt1 - Receiver waits for a falling edge on the RC7/RX/DT pin to wake from sleep.0 - Receiver operates normally.Bit 0: ABDEN — Reset Baud – auto-baud recalculation on next character (async only)1 - Auto-baud detect mode is enabled. Bit is automatically cleared on baud rate detect.0 - Auto-baud detect mode is disabled.
12Transmitter Set Baud: BRGH (TXSTA) & BRG16 (BAUDCTL) TXEN = 1: Enable transmitter (TXSTA)SPEN = 1: Enable Serial Port (RCSTA)TX/CK pin is outputSYNC: Synchronous-1 or Asynchronous-0 (TXSTA)TXREG: Write data to be sent here.TSR: Data automatically transferred to TSR shift register from which it is serialized and output.TXREG is cleared and awaits new data to repeat transmission.
13Receiver Set Baud: BRGH (TXSTA) & BRG16 (BAUDCTL) CREN = 1: Enable receiver (RCSTA)SPEN = 1: Enable Serial Port (RCSTA)Input to RX/DT pinSYNC: Synchronous-1 or Asynchronous-0 (TXSTA)RX/DT serial pin data sent to RSR shift register.RCREG: 8 or 9-bit data from RSR automatically transferred here.Input data will be readable from RCREG register.
14TX/RC Interrupts Interrupt represents each successive byte. Transmit Enable TXIE or RCIE to enable interrupt.TransmitWhen TXREG is empty, TXIF flag is set.FlagInterrupt: Send to TXREGTXIF is reset until TXREG is re-emptied.ReceiveUpon filling RCREG, RCIF flag is set.FlagInterrupt: Read RCREGRCIF flag is reset until RCREG is re-filled.
16Example Code Utilizing data received by EUSART. Interrupt RoutineIf RCIF flag is set, read EUSART (RCREG).Flag code when read.Main function:Enable interrupt.Endless loop. If flagged, read new data and place in array.
18Errors Framing Error: In asynchronous mode Overrun Error Stop bit not received at expected time.Enables FERR bit (RCSTA).Interrupt not necessarily generated, simply informs of possibly incorrect data.FERR is cleared by once data is read.Overrun ErrorRCREG is FIFO and can hold no more than two bytes.Third byte while RCREG is still fullEnables OERR bit (RCSTA).No more data received until OERR is manually cleared (clear CREN).Manual clearing of SPEN (RCSTA) will reset entire EUSART.