1. ASIC Review 2014 1 DCD

2. ASIC Review 2014 2 DCD is implemented in UMC 0.18 um CMOS technology 3.2mm x 5mm DCD-B uses bump bonding on the UMC technology provided by EuroPractice. DCD has 256 analog channels each housing an input stage and ADCs (1 pipeline or 2 cyclic).

3. ASIC Review 2014 3 DCDBPip ADC TIA 200 µm 5 mm

4. ASIC Review 2014 4 The analog input stage performs various tasks. Keeps voltage constant, amplification, shaping, CM correction, pedestal correction The analog signal is digitized using current-mode cyclic or pipelined ADCs A large synthesized digital block decodes and derandomizes the ADC raw data which are then transmitted in a well sorted sequence to the DHP chips using fast parallel 8-bit digital outputs.

5. ASIC Review 2014 5 DCD Block

6. ASIC Review 2014 6 Analog Part with cyclic ADC

7. ASIC Review 2014 7 Analog Part with pipelined ADC

8. ASIC Review 2014 8 Current-receiver based on a trans-impedance amplifier with a resistor on its output that amplifies the DEPFET current. Two current-mode cyclic ADCs (ADCR and ADCL) based on current-memory cells (CMC). Two-bit DAC for pedestal correction. Decoder for generating of the control signals for the ADC.

9. ASIC Review 2014 9 The hearth of the block is a trans-impedance amplifier A ”bleeding resistor” Rs is connected between Vout and the input of the ADC. Since the ADC holds its input at a constant potential, the current flowing into the ADC is proportional to Iin The amplifier can operate in the mode to suppress common mode variations and amplify only the difference from the common mode signal. Novel voltage-drop insensitive current sources with enclosed NMOS transistors have been used for sensible currents like ISF

10. ASIC Review 2014 10 Signal receiver

11. ASIC Review 2014 11 Common mode operation

12. ASIC Review 2014 12 Single-Input Amplifier The single input amplifier is not able to distinguish between signal and crosstalk Amplifier bandwidth quite high ~ 100Mhz/2  12 ADC Crosstalk sources: Switching of DEPFET rows Fluctuations in power supply voltages EM environment Assumption: crosstalk affects all channels equally – “common mode noise” 5cm

13. ASIC Review 2014 13 Differential Amplifier Differential amplifiers are not sensitive to common signals. 13 ADC + + Output common mode feedback Input common mode feedback

14. ASIC Review 2014 14 Differential Amplifier Problem: DEPFET signal is not differential. Idea: feed two DEPFET signals to a differential amplifier. Drawback: double hits are not amplified. 14 ADC + + Hit

15. ASIC Review 2014 15 New: Multi-differential Amplifier Idea: extend the differential scheme to n inputs. The inputs are connected to n DEPFET rows. The amplifier is not sensitive common signals. 15 ADC + +

16. ASIC Review 2014 16 New: Multi-differential Amplifier The amplifier amplifies the difference from the mean value. In the case of large n, the mean value is not influenced by single hits. Behaves as the single input amplifier for the case of sparse signals. 16 ADC + +

17. ASIC Review 2014 17 The ADC uses redundant signed-digit (RSD) conversion. The algorithm starts with the comparison of the input signal with two thresholds, one positive and one negative. If the input signal is larger than the positive threshold, the pair of output code bits is set to 10, meaning +1, and a reference current is subtracted. If the input signal is lower than the negative threshold, the output code is set to 01 (-1) and the reference is added. If the input signal value is between the thresholds, the bits are set to 00 (0) and no arithmetical operation is carried out. The residue signal is multiplied by two and the result undergoes the same operation for the next bits. The conversion is not inuenced by the comparator osets, providing the osets are not larger than half of the threshold. Current-mode memory cells are used to implement the described A/D conversion algorithm.

18. ASIC Review 2014 Sw2 A TC 21 3 CfCf Sw1 Sw2 4 21 Sw1 Wr Wr+Rd WrWr+Rd T1 I1 IO I in /I out V GS Ref Ref2 C A I in /I out

19. ASIC Review 2014 wrrrnc lt ncccwr nc lt rdlt rd wrncrr rdlt rd ncwrcc rrnc rd lt ncccwr rd lt rdlt rd wrncrr rdlt rd ncwrcc SS 2(S-h 0 R+l 0 R) 2(2(2(2(S - h 0 R + l 0 R) - h 1 R + l 1 R) – h 2 R + l 2 R) – h 3 R + l 3 R) = Res wrrrnc lt S‘ h0h0 l0l0 h1h1 l1l1 h2h2 l2l2 h3h3 l3l3 sample state 1sample state 2state3state4 state1state2state3state4sample state 1 2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R) 2(2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R)–h 2 R+l 2 R) memory cell comparator rd – read wr – write nc – not connected r – reset c – compare lt - latched States: 1.2. 3.4. 1.2. 3.4. ck2ck1ck3ck4 ck6ck5ck7ck8ck9 Res

20. ASIC Review 2014 20 ADC

21. ASIC Review 2014 21 Current memory cell Sw1 Sw2 Sw4 A TC DAC 24 μ A SF Sub Add WrB* WrB NotRd AmpLow 24 μ A 12 μ A Logic Cmp1Cmp2 ThHiThLo Rd 3 1 I in RefFB RefIn CfCf 2 En RefIn 4 Wr* VFBPBias VFBNBias (VPSource2) VFBNCasc VPSource VAmpPBias VPSourceCasc Sw3 NotWr NotRd AND Not Wr Sw5 RefIn RefNWELL

22. ASIC Review 2014 22 Comparator Vbias 24 μ A Th ResB Gate AmpLow ResBLB RefIn 24 μ A 6X2 μ A 12 μ A Comp In Or th VNMOSVPMOS IFBP IFBN TP1TP2

23. ASIC Review 2014 23 Global bias block

24. ASIC Review 2014 24 Slow control

25. ASIC Review 2014 25 TCUM1 first implementation of the cyclic ADC based on current memory cells (CMC) – too slow and too large TCUM3 improved (for speed) implementation of the cyclic and pipelined ADC with CMCs – too large DCD1 72-channel readout chip for DEPFET – small cyclic ADCs (2/channel) and regulated cascode as receiver – 80ns sampling time and proper size – too high noise due to crosstalk DCD2 – fixed crosstalk problem (constant current consumption) – INL ~3.5 in some channels and noise ~50nA at 100ns sampling time DCDB1 256-channel chip with Belle II size – cyclic ADCs from DCD2 and transimpedance amplifers – works but noise a bit high at 100ns sampling time (120nA) DCDB2 – noise improved ~ 60nA at full speed – INL about 4 LSB in some channels DCDB4 cyclic – improved DCDB2 not tested yet DCDB pipelined – noise ~ 45nA at full speed – INL about 2.5 LSB (sometimes some channels have long codes) We believe, the problem has been understood and can be solved by resizing of transistors Still to be decided – should we use cyclic or pipelined version or both We need more measurements Measurements of DCD cyclic DC characteristics measurements

26. ASIC Review 2014 26 Test all ADCs Test results on DCD pipeline ADC gain 72nA/LSB (~110e @ gq 650pA/e) Noise: ~0.55LSB (60e @ gq 650pA/e) 275e 220e