1. Sima Dezső 2007 őszi félév (Ver. 2.1)  Dezső Sima, 2007 Többmagos Processzorok (3)

2. Dual-Core Xeon UP-lines 10.1.3 Dual/quad-core server processors Dual/Quad-Core Xeon DP-lines Dual-Core Xeon MP-lines

3. Xeon 3000 - line Core 2 Duo 60 nm 9 /200 6 Dual-Core Xeon UP-lines 10.1.3 Dual/quad-core server processors (Core based, monolithic, dual-core)

4. Table: Main features of the dual-core Xeon 3000 UP-line [1.8], [1.9] Xeon 3000 line (1) Series 3000 (Conroe) Dual/Quad-CoreDC Models3040-3070 MicroarchitectureCore CoresE6300-E6700 Intro.9/2006 Technology65 nm Die size143 mm 2 Nr. of transistors291 mtrs f c [GHz]1.86-2.66 L22*4 MB FSB [MT/s]1066 TDP [W]65 SocketFC-LGA6 EM64T HT ED VT EIST La Grande AMT2 10.1.3 Xeon 3000 UP-line (Conroe)

5. 10.1.3 Dual/quad-core server processors Xeon DP 2.8Paxville DP90 nm 10/2005 Xeon 5000 line Dempsey65 nm 5/2006 Dual/Quad-Core Xeon DP-lines Xeon 5100 lineWoodcrest65 nm 6/2006 Xeon 5300 line Clovertown65 nm 11/2006 (Netburst based, multi-chip, two Irwindale cores) (Netburst based, multi-chip, two Cedar Mill cores) (Core based, monolithic, dual-core) (Core based, multi-chip, two Woodcrest chips)

6. http://www.xbitlabs.com/articles/cpu/display/opteron-xeon-workstation_5.html Nocona Paxville IrwindaleNocona (L2 enlarged to 2MB) (2 x Irwindale cores) 6/2004 10/2004 90 nm 112 mm 2 125 mtrs Xeon DP 2.8 – 3.4 Xeon DP 2.8J - 3.4J mPGA 604 2/2005 9/2005 90 nm 135 mm 2 169 mtrs Xeon DP 2.8 – 3.6 Xeon DP 3.8 mPGA 604 10/2005 11/2005 90 nm 2 x 135 mm 2 2 x 169 mtrs Xeon DP 2.8 Xeon MP 7020-7041 mPGA 604 Figure: Genealogy of the Xeon Paxville core (DP enhanced Prescott)(DP enhanced Prescott 2M) http://www.theinquirer.net/default.aspx?article=16879 http://www.gamepc.com/labs/view_content.asp?id=x36o252&page=2 Sources: Intel’s first 64-bit Xeon In contrast: corresponding desktop processors have the LGA 775 socket. 10.1.3 Xeon DP 2.8 (Paxville DP) (1)

7. Heat Sink Die FC-mPGA4 package Pin side capacitors Package pin Die size capacitors Figure: Packaging of the Paxville processor The FC-mPGA package interfaces with the motherboard via an mPGA604 socket Source: - „Dual-Core Intel Xeon Processor 2.80 GHz Datasheet,” Oct. 2005, http://download.intel.com/design/Xeon/datashts/30915801.pdf 10.1.3 Xeon DP 2.8 (Paxville DP) (2)

8. Figure Connecting the two Irwindale cores in the large Paxville Package (?) [1.3] 10.1.3 Xeon DP 2.8 (Paxville DP) (3)

9. Source: Conolly C., „Intel Paxville Dual Core Xeon and the ASsus PVL-D Intel 7520,” Oct. 2005, http://www.gamepc.com/labs/view_content.asp?id=paxville&page=1 Figure: Packaging of the Paxville (two Irwindale dies are mounted on a carrier and the carrier is packaged as a 604 package” 10.1.3 Xeon DP 2.8 (Paxville DP) (4)

10. Table: Dual-Core Xeon DP-lines (1) [1.8], [1.9] 10.1.3 Xeon DP 2.8 (Paxville DP) (5) PGA 604 135 800 2*2 MB 2.8 2*169 mtrs 2*135 mm 2 90 nm 10/2005 2*Irwindale dies Netburst Xeon DP 2.8 DC (Paxville DP) AMT2 La Grande EIST VT ED HT EM64T Socket TDP [W] FSB [MT/s] L2 f c [GHz] Nr. of transistors Die size Technology Intro. Cores Microarchitecture Models Dual/Quad-Core Series

11. Figure: Block diagram of the Dempsey (Cedar Mill-based) Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf 10.1.3 Xeon 5000 DP-line (Dempsey) (1)

12. http://www.tecchannel.de/_misc/img/detail1000.cfm?pk=342850&fk=432919&id=il-74145482909021379 Figure: Packaging of the Dempsey 10.1.3 Xeon 5000 DP-line (Dempsey) (2)

13. Figure: The Xeon DP Dempsy with the two FB capable Blackford chipset [1.2] 10.1.3 Xeon 5000 DP-line (Dempsey) (3)

14. Table: Dual-Core Xeon DP-lines (2) [1.8], [1.9] 10.1.3 Xeon 5000 DP-line (Dempsey) (4)

15. Figure: Block diagram of the Merom, Conroe and Woodcrest processors Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf 10.1.2 Xeon 5100 DP-line (Woodcrest) (1)

16. Figure: Die shot of the Woodcrest (5100 series) processor (L2: 4 MB) Source: http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg Woodcrest 10.1.3 Xeon 5100 DP-line (Woodcrest) (2)

17. Sources: Kubicki K., „Intel 2006 Mobile CPU Roadmap Update,” Mai 2006,Intel 2006 Mobile CPU Roadmap Update http://www.dailytech.com/Article.aspx?newsid=2546 Conroe Merom Hübner, T., „Intel Core 2 Duo E6700 und E6600,” July 2006, http://www.computerbase.de/artikel/hardware/prozessoren/2006/test_intel_core_2_duo_e6700_e6600/1/ Figure: Contrasting the die shots of Merom, Conroe and Woodcrest Woodcrest http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg 10.1.3 Xeon 5100 DP-line (Woodcrest) (3)

18. Table: Dual-Core Xeon DP-lines (3) [1.8], [1.9] 10.1.3 Xeon 5100 DP-line (Woodcrest) (4)

19. Figure: The Xeon 5300 series (Clovertown) dies are built up of two dual core Woodcrest [1.4] 10.1.3 Xeon 5300 DP-line (Clovertown) (1)

20. Source: Wasson S., „Intel’s Woodcrest procdessor previewed,” May 2006, http://techreport.com/etc/2006q2/woodcrest/index.x?pg=2 Figure: Packaging the Clowertown 10.1.3 Xeon 5300 DP-line (Clovertown) (2)

21. Table: Dual-Core Xeon DP-lines (4) [1.8], [1.9] 10.1.3 Xeon 5300 DP-line (Clovertown) (3)

22. 10.1.3 Dual/quad-core server processors Xeon 7000 linePaxville MP90 nm 11/2005 Xeon 7100 line Tulsa65 nm 8/2006 Dual-Core Xeon MP-lines (Netburst based, multi-chip, two Irwindale dies) (Netburst based, monolithic, Cedar Mill based)

23. Table: Dual-Core Xeon MP-lines (1) [1.8], [1.9] 1 Concerning the L2 cache size, there is a contradiction in Intel’s documentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches. Xeon 7000 line (Paxville MP) (1) 10.1.3 Xeon 7000 MP-line (Paxville MP) (1) AMT2 La Grande EIST VT ED HT EM64T PGA604Socket 95/150TDP [W] 667/800FSB [MT/s] L3 2*1/2 MB 1 L2 2.66-3.0f c [GHz] 2*169 mtrsNr. of transistors 2*135 mm 2 Die size 90 nmTechnology 11/2005Intro. 2*Irwindale diesCores NetburstMicroarchitecture 7020-7041Models DCDual/Quad-Core 7000 (Paxville MP) Series

24. Figure: Block diagram and die shot of Tulsa [1.5] 10.1.3 Xeon 7100 MP-line (Tulsa) (1)

25. Figure: Detailed block diagram of Tulsa (Cedar Mill-based) Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf 10.1.3 Xeon 7100 MP-line (Tulsa) (2)

26. Figure: Die shot of Tulsa (L3: 16 M) Source: Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/ 10.1.3 Xeon 7100 MP-line (Tulsa) (3)

27. (81 mm 2 ) (435 mm 2 ) Cedar Mill Tulsa 2 x 1 MB L” + 16 MB L3 2 x 2 MB L2 Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/ Sources: Huynh T., „Pressler: Intel Extreme Edition 955,” Dec. 2005, http://www.sudhian.com/index.php?/articles/show/pressler_intel_extreme_edition_955_prescotts_last_hurrah/, Figure: Contrasting the Cedar Mill and Tulsa die shots 10.1.3 Xeon 7100 MP-line (Tulsa) (4)

28. Table: Dual-Core Xeon MP-lines (2) [1.8], [1.9] 1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches. AMT2 La Grande EIST VT ED HT EM64T PGA604 Socket 95/150 TDP [W] 667/800 FSB [MT/s] 4/8/16 MBL3 2*1 MB2*1/2 MB 1 L2 2.5-3.52.66-3.0f c [GHz] 1328 mtrs2*169 mtrsNr. of transistors 435 mm 2 2*135 mm 2 Die size 65 nm90 nmTechnology 8/200611/2005Intro. Cedar Mill-based single die2*Irwindale diesCores Netburst Microarchitekture 7110M-7140M / 7110N-7150N7020-7041Models DC Dual/Quad-Core 7100 (Tulsa) 7000 (Paxville MP) Series 10.1.3 Xeon 7100 MP-line (Tulsa) (5)

29. CategoryCode NameCoresCacheMarket DesktopKentsfield Dual core multi-die 4 MBMid 2007 DesktopConroe Dual core single die 4 MB sharedEnd 2006 DesktopAllendale Dual core single die 2 MB sharedEnd 2006 DesktopCedar Mill (NetBurst/P4)Single core512 kB, 1 MB, 2 MBEarly 2006 DesktopPresler (NetBurst/P4)Dual core, dual die4 MBEarly 2006 Desktop/MobileMillvilleSingle core1 MBEarly 2007 MobileYonah2Dual core, single die2 MBEarly 2006 MobileYonah1Single core1/2 MBMid 2006 MobileStealeySingle core512 kBMid 2007 MobileMeromDual core, single die2/4 MB sharedEnd 2006 EnterpriseSossamanDual core, single die2 MBEarly 2006 EnterpriseWoodcrestDual core, single die4 MBMid 2006 EnterpriseClovertownQuad core, multi-die4 MBMid 2007 EnterpriseDempsey (NetBurst/Xeon)Dual core, dual die4 MBMid 2006 EnterpriseTulsa Dual core single die 4/8/16 MBEnd 2006 EnterpriseWhitefield Quad core single die 8 MB, 16 MB sharedEarly 2008 Figure 5.7: Future 65 nm processors (Overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered 10.1.3 Guessed road map of Intel processors (1)

30. CodenameCoresCacheMarket DesktopWolfdaleDual core, single die3 MB shared2008 DesktopRidgefield Dual core single die 6 MB shared2008 DesktopYorkfield 8 cores multi-die 12 MB shared2008+ DesktopBloomfieldQuad core, single die-2008+ Desktop/Mob ile PerryvilleSingle core2 MB2008 MobilePenryn Dual core single die 3 MB, 6 MB shared2008 MobileSilverthorne--2008+ EnterpriseHapertown 8 cores multi-die 12 MB shared2008 Figure 5.8: Future 45 nm processors (overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered 10.1.3 Guessed road map of Intel processors (1)

31. Source: Thrax, „ Core 2 Duo and the future of Intel,” Nov. 2006, http://www.short-media.com/review.php?r=343 Figure: Roadmap of Intel’s lines 10.1 Published road map of Intel processors

32. Dual-core Itanium 2 Montecito 90 nm 7 /200 6 Quad-core Itanium 2 Tukwila 65 nm 2008 Dual/quad-core Itanium 2 lines 10.1.4 Dual/quad-core Itanium processors (Itanium 2 based, monolithic)

33. Figure: Block diagram and basic floor plan of the Montecito [1.5] 10.1.4 Dual-core Itanium 2 (Montecito) (1)

34. 10.1.4 Dual-core Itanium 2 (Montecito) (2) Figure: Block diagram of the Itanium 2 processor [1.12]

35. 10.1.4 Dual-core Itanium 2 (Montecito) (3) McNairy C. and Bhatia R., „Montecito,” IEEE Micro, March-April 2005, pp. 10-20 Figure: Block diagram of the Montecito

36. 10.1.4 Dual-core Itanium 2 (Montecito) (4) Figure: New features of Montecito Source: Intel

37. Figure: Floor plan of Montecito [1.14] Core 10.1.4 Dual-core Itanium 2 (Montecito) (5)

38. Madison (130 nm) Montecito (90 nm) L2: 256 KB, L3: 9 MB L2I: 1 MB, L2D: 256 KB, L3: 12 MB (Inthe figure reduced to 90 nm) Figure: Contrasting Itanium 2 Madison and Montecito (at the same feature size) [1.14] Further source: Krewell K., „Best Servers of 2004,” Microprocessor Report, Jan. 2005, http://h10018.www1.hp.com/wwsolutions/misc/docs/2004_Server_Processor_of_Year.pdf 10.1.4 Dual-core Itanium 2 (Montecito) (6)

39. Source: DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf Figure: Contrasting die sizes and floor plans of Itanium processors 10.1.4 Dual-core Itanium 2 (Montecito) (7)

40. Table: Main features of the dual-core Itanium 2 line [1.8], [1.9] 10.1.4 Dual-core Itanium 2 (Montecito) (8)

41. Figure: Expected features of the quad-core Tukwila [1.8] 10.1.5 Quad-core Itanium 2 (Tukwila) (1)

42. Figure: Preliminary die shot of Tukwila [1.11] 10.1.5 Quad-core Itanium 2 (Tukwila) (2)

43. 10.1 Literature (1) x86 multicore processors [1.6] Shimpi A. L. and Wilson D., Intel Pentium 4 6xx and 3.73EE,” Febr. 2005, http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2353&p=3 [1.7] Smith, S.L. and Valentine, B.:”Intel Core Microarchitecture,” March 2006, http://download.intel.com/pressroom/kits/press/core2/ NGMA%20IDF%20Press%20Mar%208%20PDF%20Set.pdf [1.3] Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,” http://www.hotchips.org/archives/hc17/3_Tue/HC17.S8/HC17.S8T1.pdf [1.2] Brookwood N., The Role of intellignet Desing in the Evolution of Multi-Core Processors,” Febr. 2006. http://www.insight64.com/downloads/IntelligentDesign.pdf [1.4] Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,” http://idfemea.intel.com/moscow/download/keynotes_and_tis/Li_Babayan_en.pdf [1.1] Bhandarkar D. „Energy Efficient Performance: The Next Frontier,” Oct. 2006, http://download.intel.com/technology/eep/fall_microprocessor_forum_2006.pdf [1.5] Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf [1.8] - Related Intel Datasheets, http://www.intel.com/design [1.9] - Wikipedia

44. 10.1 Literature (2) Montecito [1.16] Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf [1.14] Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,” Proc. ISSCC, 2005, pp. 182-183, [1.10] DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf [1.11] Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004, http://www.decus.de/sig/vms/TUD_2004/INTEL.PDF [1.12] McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp. 44-55 [1.15] Naffziger S. et al., The Implementation of a 2-Core, Multi-threaded Itanium Family Processor, IEEE Journal Solid-State Circuits, Vol. 41, No. 1, Jan. 2006, pp. 197-209 [1.17] - „Inside the Intel Itanium 2 Processor,” Technical White Paper, July 2002, HP Corp. [1.18] - Related Intel Datasheets, http://www.intel.com/design/itanium2/documentation.htm [1.13] McNairy C. and Bhatia R., „Montecito: A Dual-Core, Dual-Thread Itanium Processor,” IEEE Micro, March-April 2005, pp. 10-20