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Over voltage protection of the Power Supply System for the PXD detector. 4-6 February 2013 Wetzlar1 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow.

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Presentation on theme: "Over voltage protection of the Power Supply System for the PXD detector. 4-6 February 2013 Wetzlar1 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow."— Presentation transcript:

1 Over voltage protection of the Power Supply System for the PXD detector. 4-6 February 2013 Wetzlar1 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 1.Some definitions - voltage transient and power surge. 2.LT4356-1, LT4356-3 Surge Stoppers from LINEAR TECHNOLOGY 3.Transient Voltage Suppression (TVS) diodes 4.Prototyping PCB 5.Tests and results 6.Plans for 2013

2 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 2 Over voltage and over current can occur because of: - failures of the Power Suppies - lightning - switching transients - inductive kickback – inductive load - shorts and other problems in power wiring What are transients and surges ? Transients as being very fast, but with low total energy < 8.4 ms Surges being slow, prolonged, and with high total energy > 8.4 ms DEPFET we protect from: -failures of the power supply – surges - -transient from fast load varation

3 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 3 Principle of suppression: A blocking device detects excessive current flow, and increases its resistance sharply to hold the load current below some limit. A shunting device detects excessive voltage, and switches to a low impedance state so that the excess current goes through it, and not through the load.

4 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 4

5 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 5 Transient Voltage Suppression Diode Application Notes

6 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 6 Sensitive are DHP and DCD chips for over voltage. Negative Voltages

7 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 7

8 OVP test board – 12 channels protected. Two-layers board. Without monitoring and control analog digital steering gate is bypassed 4-6 February 2013 Wetzlar8 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

9 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 9 Voltage Regulator OVP PCB Load Test setup

10 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 10 Voltage Regulator Front End sense power 15 m Simplified layout of one channel OVP Module 1.8V/2.3A

11 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 11 Load sense TMR Fault Timer Input Differential Amplifier Schematic of over voltage protection channel

12 4-6 February 2013 Wetzlar12 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow „for short transient in duration”

13 4-6 February 2013 Wetzlar13 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow „for long transient in duration”

14 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 14 Digital Domain Analog Domain Gate Domain Steering Domain Xilinx CPLD uC signals Digital optocouplers Small, SMD optocouplers are not common. Status bits are sent to the uC, reset (re-enable) bits are sent to the channels. Should we latch error signal “in the channel” or in the Xilinx (with enable-disable option) ? Digital control of the Over Voltage Protection board Can the reset (re-enable) signals be common for the single domain ?

15 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 15 What next ? 1.to test prototype with PS system – some channels 2.design next prototype which will fit to last version 3.PCB 4.integration with PS System

16 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 16 Thank you Dankscheen Xie xie Arigato Danke Dekuji Dziekuje Gracias

17 Backup 4-6 February 2013 Wetzlar17 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

18 LT1970 Power Op LT1809 Low Distortion Op Amps LT4356-3 Surge Stopper with Fault Latchoff Front End Electronics 4-6 February 2013 Wetzlar18 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow LTspice Symulation

19 input load voltage or current fault 4-6 February 2013 Wetzlar19 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

20 4-6 February 2013 Wetzlar20 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

21 DVDD DCD 1.8V/1A DHPCORE 1.2V/580mA DHPIO 1.2V DVDD SW 3.3V/24mA from Voltage Regulator to Front End Electronic FAULT(3.5V) UNDERVOLTAGE FAULT (1.6V) UNDERVOLTAGE FAULT(3.5V) UNDERVOLTAGE FAULT UNDERVOLTAGE 4-6 February 2013 Wetzlar21 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow Digital Domain Digital_Ground DGND

22 AVDD DCD 1.8V/2.3A REFIN DCD 1.1V/360mA AmpLow 0.35V/-1A VSOURCE 0V to 7V/100mA from Voltage Regulator to Front End Electronic FAULT(3.5V) UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE 4-6 February 2013 Wetzlar22 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow Analog Domain Analog_Ground AGND

23 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 23 GATE ON 1,2,3 -3V to -13V / 60mA GATE OFF -3V to +5V / 60mA VCCG 1,2,3 -10V to+1V / 10mA from Voltage Regulatorto Front End Electronic FAULT(30 V) UNDERVOLTAGE FAULT(10 V) UNDERVOLTAGE FAULT UNDERVOLTAGE Gate Domain Gate_Ground GGND

24 4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 24 CLEAR ON 7V to 25V / 60mA CLEAR OFF 0V to 5V / -60mA VBULK 5V to 15V / 10mA VBP (back plane) -20V from Voltage Regulatorto Front End Electronic FAULT(30 V) UNDERVOLTAGE FAULT(10 V) UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE Steering Domain VGUARD -7V to 0V FAULT UNDERVOLTAGE Steering_Ground SGND VDRIFT -12V to -5V SUB SUB+3.3V 0.06mA

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