1. Microprocessors 3 Buses, Addresses and Machine Cycles 1 Modified April 2011 ©Paul R. Godin prgodin ° @ gmail.com

2. Buses The data bus is bi-directional and is responsible for transporting data between the  P and the peripheral devices. The address bus identifies the location of the peripheral device or memory location. Address buses are unidirectional. The bits flow from the MPU to the devices. The control buses are unidirectional. Each has a unique function. They are used to control operations and indicate status. Examples include buses to enable or tristate devices on the common bus, or to indicate when a process is complete. 2

3. Multiplexing Multiplexing is defined as utilizing a bus for several functions. MPUs and other similar devices often multiplex their address bus: –The first grouping of address bits, or lower address, (example: AD 0 to AD 7 ) are alternately used for address and data bits. –The upper address bus, or high-order addresses (example: A 8 to A 15 ), are not multiplexed and are unidirectional. Question: why multiplex? 3

4. Demultiplexing An external demultiplexeing system is used to separate the address output from the data output of the AD bus. An external register latches onto the address and holds it. A control signal called the ALE (Address Latch Enable) provides an output pulse to cause the external register to latch onto the lower address. The following slides shows an example… 4

5. Sequence for Demux The microprocessor provides a 16-bit address (such as a Fetch cycle) –A Lower 8-bit on the AD bus (Address-Data) –A Higher 8-bit on the A bus (Address) The ALE (Address Latch Enable) outputs a pulse indicating that the lower 8-bits are address. The lower address is saved in a PIPO register (the ALE provided the edge required). The Microprocessor then uses the lower 8-bits as data 5

6. Upper Address Bus Lower Address Bus Data Bus Microprocessor 6 Microprocessor shares the Lower Address Bus with the Data Bus

7. Upper Address Bus Lower Address Bus Data Bus Microprocessor 7

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13. Example of buses of a basic micro 13

14. Control Buses To avoid bus contention problems, only a single device is enabled at a time, Devices are enabled/disabled via tri-stateable outputs Control: In peripheral-mapped I/O, the I/O is enabled through the use of control lines. In memory-mapped I/O, the I/O is enabled through the use of address ranges (external decoder required). 14

15. Decoding an Address in Memory- Mapped I/O 15 Address 16-bit Upper 3 bits A 15 A 13 3 to 8 Decoder A B C Y0Y0 Y1Y1 Y2Y2 Y3Y3 Y4Y4 Y5Y5 Y6Y6 Y7Y7 Individual Device Enables

16. Timing Diagrams 16

17. Basic Function of a Microprocessor Microprocessors fetch an instruction and execute that instruction. The cycle is repeated. Microprocessors use a variety of bus connections to locate values, move data, and to enable or disable devices. Fetch Execute 17

18. Timing Diagrams Timing diagrams in microprocessor systems are a little different from traditional digital timing diagrams. There are many, many more combinations of inputs and outputs, therefore the individual lines that make up the data bus are not usually included in the timing diagram. Combined lines are indicated with a 18

19. Bus Timing Diagrams Timing diagrams for bus operations can be difficult to manage. –With so many connections, the diagrams may become unmanageable. –Outputs aren’t addressed on a value-by-value basis. The actual values are based on the instructions and data controlled by the micro system. Timing diagrams for bus systems focus on timing of groups of signals rather than the results of individual inputs and outputs. 19

20. Bus Timing Diagrams Address and data buses are represented this way: Float or don’t care state Binary value 1 Binary value 2 Float or don’t care state 20

21. Machine Cycles Microprocessors follow a pattern when fetching and executing instructions and performing read and write processes. These patterns are called machine cycles and are usually identified by M 1, M 2, etc …. 21 8085 Specification Sheet

22. T-States The clock provides edges to the microprocessor The microprocessor circuitry converts these edges to another clock called a “T-State”. This is the standard clock for most operations in a computer. 22

23. M 1 : Opcode Fetch Cycle The first cycle is the Fetch cycle, or M 1. 23

24. M 1 T 1 At M 1 T 1, the first clock pulse indicates that the lower multiplexed address/data bus is providing an address. ALE goes high, then provides a negative edge in the middle of the cycle for the external latch. 24 T 1 is used to demux the AD bus

25. M 1 T 2 At M 1 T 2, the lower address has already been latched. The read (RD’) is active and the instruction is placed on AD 0 to AD 7. 25

26. M 1 T 3 At M 1 T 3, the instruction from memory is on AD 0 to AD 7 and is read into the microprocessor’s register. 26

27. M 1 T 4 At M 1 T 4, the instruction is processed by the microprocessor and the AD 0 to AD 7 are in a high impedance state. 27

28. M 2: Memory Read Cycle The second cycle to discuss is the memory read cycle. 28

29. M 2 T 1 Just prior to M 2 T 1, the Program Counter increments the address by 1 (PC+1). The lower address bus is latched by ALE. 29 T 1 is used to demux the AD bus

30. M 2 T 2 At M 2 T 2, the read is active (RD’). On the rising edge of T 2 the data bus is now an input bus to the MPU. 30

31. M 2 T 3 At M 2 T 3, the MPU reads and stores the byte in the ACC register. 31

32. M 3: Memory Write Cycle The memory write cycle is required to provide processed data from the microprocessor to either the memory or I/O devices. 32

33. M 3 T 1 At M 3 T 1, the MPU provides the IO address. The lower order address is latched by the falling ALE edge. 33 T 1 is used to demux the AD bus

34. M 3 T 2 At M 3 T 2, the write has been enabled and the decoder has enabled the proper I/O IC to read the data that is now on the AD bus. 34

35. M 3 T 3 At M 3 T 3, the active-low write is disabled and the microprocessor is ready for the next instruction. 35

36. 1 st Approximation First approximation is when one estimates the approximate amount of “T-States” needed for each cycle. Using the First Approximation method, the following is assumed: –All Fetch Cycles = 4 T-States –All ALU Functions with No Bytes = 1 MC = 4 T-States –All 1 byte Functions with 1 Byte = 2 MC = 7 T-States (4+3) –All 2 byte Functions with 2 Byte = 3 MC = 10 T-States (4+3+3) 36

37. End of Part 3 37 ©Paul R. Godin prgodin ° @ gmail.com