1. WINLAB Open Cognitive Radio Platform Architecture v1.0 WINLAB – Rutgers University Date : July 27th 2009 Authors : Prasanthi Maddala, prasanthi.m@gmail.comprasanthi.m@gmail.com Khanh Le, kle@winlab.rutgers.edukle@winlab.rutgers.edu Ivan Seskar, seskar@winlab.rutgers.eduseskar@winlab.rutgers.edu

2. OCRP Architecture 2 SDR Tx The SDR Tx takes either Control or Data Commands. These commands are sent as IP packets.

3. OCRP Architecture 3 SDR Tx Architecture Wibo SPI Application Block Dibo SPI DAC Interface wibo_sen wibo_sclk wibo_sdata wibo_u2_sen radio_io5 radio_io6 radio_io7 dibo_sdata dibo_sclk dibo_sen tx_sync tx_data other outputs Rx Ethernet Interface Buffer System Controller Memory Control Command FIFO Command Descriptor Generator

4. OCRP Architecture 4 Frame Format Control Frame Application Code[4:0] Type [2:0] 00000 - DIBO 000 – Sys Control 00001 - WIBO 001 – App Control 00010 - Tx Application 010 – App Data 00011 – Rx Application Sequence Number : A number given by the user to each frame to keep track of the commands that have been processed and that have been dropped.

5. OCRP Architecture 5 Data Frame

6. OCRP Architecture 6 Rx Ethernet Interface The Rx Ethernet Interface detects an Ethernet frame by looking at the preamble and forwards the Ethernet payload to the next block. It sends out data as 32 bit words and also sends start of frame, end of frame and data valid signals for the next block to sync up.

7. OCRP Architecture 7 Rx Ethernet Interface – FPGA Top IF Signal NameIn/OutWidthDescription eth_data_validIn1Active High. Indicates that the data on eth_data port is valid. eth_errorIn1 eth_dataIn8Ethernet frame data that comes from Ethernet PHY module on the board. For an Ethernet link at 100Mbps only eth_data[3:0] is valid. If it is a 1Gbps link all the 8 bits are valid.

8. OCRP Architecture 8 Signal NameIn/OutWidthDescription SofOut1Start-of-frame signal, indicating first word of payload. EofOut1End-of-frame signal, indicating last word of payload. dataOut32Ethernet payload data data_validOut1Active High. Indicates that the current data word is valid. Rx Ethernet Interface – Command Descriptor Generator IF Signal NameIn/OutWidthDescription frame_errOut1Active High. Indicates that there is an error in the frame Ex: eth_error signal is high or frame is incomplete – size in the Ethernet header does not match with the actual size.(No gaps are allowed in an Ethernet frame) Rx Ethernet Interface – Register Map IF

9. OCRP Architecture 9 Command Descriptor Generator Command descriptor generator performs the following functions 1. Parses the IP header to see if the destination IP address matches. 2. Generates command descriptors for both the control and data commands and writes them to the command FIFO. 3. Writes the application data to a buffer.

10. OCRP Architecture 10 Total Length: 16-bits This field indicates the size of the datagram, including the header and the data.

11. OCRP Architecture 11 Command Descriptor Generator – Memory Control IF Signal NameIn/OutWidthDescription buf_wr_reqOut1Active high. Signal requesting the memory control for buf_wr_size bytes of space on the buffer to store data. buf_wr_sizeOut16Size of data to be stored in the buffer(bytes). It is calculated from the payload length given in the IP header. buf_wr_ackIn1Active High. Response to buf_wr_req indicating that the requested space is available at the address buf_wr_ptr. buf_wr_ack is sent as soon as buf_wr_req is detected by the memory control, i.e., the command descriptor generator can send a buffer request and check for buf_wr_ack in the next clock cycle. If buf_wr_ack is not high, it means that the requested buffer space is not available. buf_wr_ptrIn16Address at which the data would be written. This address will be inserted in the data command descriptor. sofOut1Start-of-frame for the app data to be stored. The memory control expects an sof (or a buf_wr_cancel) as soon as the buf_wr_req is pulled low. If the buf_wr_req remains low for a clock cycle or more before sending the sof, then the data write operation is ignored. eofOut1End-of-frame for the app data to be stored buf_wr_dataOut32App data word to be stored buf_data_validOut1Active High. Indicates that the data word on buf_wr_data is valid buf_wr_cancelOut1Active High. Command descriptor generator can cancel a data write operation at any time, by setting this signal high. A write operation starts when the buffer request is sent to the memory control and ends when eof is sent.

12. OCRP Architecture 12 Command Descriptor Generator – Command FIFO IF Signal NameIn/OutWidthDescription SofOut1Start-of-frame signal, indicating the first word of command descriptor EofOut1End-of-frame signal, indicating the last(second) word of command descriptor. cmd_dataOut32Command descriptor word. cmd_writeOut1Active High. Indicates that the current word on cmd_data is valid and acts a write request for the command FIFO. cmd_full_flagIn1Active High. Indicates that the command FIFO is full and can not accept any commands

13. OCRP Architecture 13 Signal NameIn/OutWidthDescription SofIn1Start-of-frame signal, indicating first word of payload. EofIn1End-of-frame signal, indicating last word of payload. dataIn32Ethernet payload data data_validIn1Active High. Indicates that the current data word is valid. Command Descriptor Generator - Rx Ethernet Interface (As defined in Rx Ethernet Interface – Command Descriptor Generator IF)

14. OCRP Architecture 14 Signal NameIn/OutWidthDescription buf_full_errOut1Active High. Indicates that the buffer is full and no more data can be accepted. cmd_full_errOut1Active High. Indicates that the command fifo is full and no more commands can be accepted. Sequence_noOut8Sequence no of the data frame which was not stored in the buffer due to a buf_full_err, or cmd_full_err, or a frame_length_err. hdr_errOut1Active High. Indicates that there is an error in the IP header – not enough no. of words ip_addr_errOut1Active High. Indicates that the destination IP address in the data frame does not match with the IP address of the board. frame_length_errOut1Active High. Indicates that the frame length calculated from IP payload length does not match with the actual frame length. In case of a control command, it might indicate that the frame length is not equal to 2 words (8 bytes). In case of a data command, if the actual frame length is more than the calculated length, only the calculated length no.of words are stored and the rest are discarded. If the actual frame length is less, the write operation is considered incomplete and is canceled. Command Descriptor Generator – Register Map IF

15. OCRP Architecture 15 Memory Control The Memory Control 1. Keeps track of available buffer space (with the help of write and read ptrs) 2. Sends an ack or nack on receiving a write request from the command descriptor generator. 3. Write ptr is updated as and when data is written to the buffer and is wrapped around once it reaches the end. 4. Read ptr is updated by incrementing the current value by last_app_size whenever the last_app_size_valid is high. When System Control receives app_done for a command it sends out the data size (last_app_size) of the command to the memory control, indicating that the buffer space can be overwritten and the read ptr be updated.

16. OCRP Architecture 16 Memory Control - Command Descriptor Generator IF (As defined in Command Descriptor Generator – Memory Control IF) Signal NameIn/OutWidthDescription buf_wr_reqIn1Active high. Signal requesting the memory control for buf_wr_size bytes of space on the buffer to store data. buf_wr_sizeIn16Size of data to be stored in the buffer(bytes). It is calculated from the payload length given in the IP header. buf_wr_ackOut1Active High. Response to buf_wr_req indicating that the requested space is available at the address buf_wr_ptr. buf_wr_ack is sent as soon as buf_wr_req is detected by the memory control, i.e., the command descriptor generator can send a buffer request and check for buf_wr_ack in the next clock cycle. If buf_wr_ack is not high, it means that the requested buffer space is not available. buf_wr_ptrOut16Address at which the data would be written. This address will be inserted in the data command descriptor. sofIn1Start-of-frame for the app data to be stored. The memory control expects an sof (or a buf_wr_cancel) as soon as the buf_wr_req is pulled low. If the buf_wr_req remains low for a clock cycle or more before sending the sof, then the data write operation is ignored. eofIn1End-of-frame for the app data to be stored buf_wr_dataIn32App data word to be stored buf_data_validIn1Active High. Indicates that the data word on buf_wr_data is valid buf_wr_cancelIn1Active High. Command descriptor generator can cancel a data write operation at any time, by setting this signal high. A write operation starts when the buffer request is sent to the memory control and ends when eof is sent.

17. OCRP Architecture 17 Memory Control – Buffer IF Signal NameIn/OutWidthDescription buf_wr_dataOut32Data word to be stored in the buffer buf_writeOut1Active high.Indicates that the word on buf_wr_data is valid buf_wr_addressOut12Address at which the data word has to be written

18. OCRP Architecture 18 Memory Control – System Control IF Signal NameIn/OutWidthDescription last_app_sizeIn16Size of the last app command (app command that has been processed) in bytes. last_app_size_validIn1Active high. Indicates that the data on last_app_size is valid

19. OCRP Architecture 19 System Control

20. OCRP Architecture 20 System Control – Command FIFO Interface Signal NameIn/OutWidthDescription SofIn1Start-of-frame signal, indicating first word of descriptor. EofIn1End-of-frame signal, indicating last word of descriptor. Cmd_dataIn32Descriptor data from Command FIFO Cmd_empty_flagIn1Command FIFO empty flag. If Cmd_empty_flag /= 1 then Command FIFO has data. Cmd_readOut1Command FIFO read signal. Cmd_read == 1 to fetch next word in queue.

21. OCRP Architecture 21 System Control - Memory Control IF Signal NameIn/OutWidthDescription last_app_sizeOut16Size of the last app command (app command that has been processed) in bytes. last_app_size_validOut1Active high. Indicates that the data on last_app_size is valid

22. OCRP Architecture 22 System Control – Tx Application Interface Signal NameIn/OutWidthDescription tx_app_param_validOut1Parameter available sync pulse. Active High for one clock cycle. tx_app_param_addrOut8Register map address field tx_app_param_dataOut24Parameter values e.g. register map values. tx_app_reqOut1Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information. tx_app_typeOut2Type of frame within Buffer : 00 – control 01 – data Others – reserved tx_app_ptrOut16Address pointer to location of data/control frames tx_app_sizeOut16Size of data/control frames tx_app_doneIn1Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.

23. OCRP Architecture 23 System Control – Rx Application Interface Signal NameIn/OutWidthDescription rx_app_param_validOut1Parameter available sync pulse. Active High for one clock cycle. rx_app_param_addrOut8Register map address field rx_app_param_dataOut24Parameter values e.g. register map values. rx_app_req (not used)Out1Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information. rx_app_type (not used)Out2Type of frame within Buffer : 00 – control 01 – data Others – reserved rx_app_ptr (not used)Out16Address pointer to location of data/control frames rx_app_size (not used)Out16Size of data/control frames rx_app_doneIn1Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.

24. OCRP Architecture 24 System Control – WIBO SPI Interface Signal NameIn/OutWidthDescription Wibo_validOut1WIBO SPI request signal Wibo_param_addrOut8WIBO SPI address field Wibo_param_dataOut23WIBO SPI data field Wibo_doneIn1WIBO SPI done signal. Indicates that the WIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI or has set the antenna switches and is ready to take in the next SPI register data.

25. OCRP Architecture 25 System Control – DIBO SPI Interface Signal NameIn/OutWidthDescription Dibo_validOut1DIBO SPI request signal Dibo_param_addrOut8DIBO SPI address field Dibo_param_dataOut23DIBO SPI data field Dibo_doneIn1DIBO SPI done signal. Indicates that the DIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI and is ready to take in the next SPI register data.

26. OCRP Architecture 26 WiBo SPI Used to configure the RF chip(MAX2829), U2,and antenna switches on wibo. No Data Commands, 1 Control Command Number of Parameters = 3 - SPI register,U2, Antenna Switches SPI register (17 : 0)

27. OCRP Architecture 27 WIBO SPI - System Control IF (As defined in System Control – WIBO SPI Interface) Signal NameIn/OutWidthDescription Wibo_validIn1WIBO SPI request signal Wibo_param_addrIn8WIBO SPI address field Wibo_param_dataIn23WIBO SPI data field Wibo_doneOut1WIBO SPI done signal. Indicates that the WIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI or has set the antenna switches and is ready to take in the next SPI register data.

28. OCRP Architecture 28 Dibo SPI Used to configure the ADC/DAC chip (AD9860) on dibo. No Data Commands, 1 Control Command Number of Parameters = 1 - SPI register SPI register (15 : 0)

29. OCRP Architecture 29 DiBo SPI - System Control IF (As defined in System Control – DIBO SPI Interface) Signal NameIn/OutWidthDescription Dibo_validIn1DIBO SPI request signal Dibo_param_addrIn8DIBO SPI address field Dibo_param_dataIn23DIBO SPI data field Dibo_doneOut1DIBO SPI done signal. Indicates that the DIBO Spi block has completed processing the command I.e., it has sent out the register data on SPI and is ready to take in the next SPI register data.

30. OCRP Architecture 30 Application Block System Control IF : 1. Application Register map values are provided using Parameter setting options e.g. app_param_valid, app_param_data 2. Data pointer and size information are provided such that App can fetch data/control information from buffer. Buffer IF : 1. App fetches buffer data without intervention from System Control. Note that buffer data could be either data or control frame.

31. OCRP Architecture 31 Application – System Control Interface (as defined in System Control – Application Interface) Signal NameIn/OutWidthDescription App_param_validIn1Parameter available sync pulse. Active High for one clock cycle. App_param_addrIn8Register map address field App_param_dataIn24Parameter values e.g. register map values. App_reqIn1Application processing request signal. Active high. This indicates that data/control frames are available within Buffer. Application shall fetch data/control information using App_type, App_ptr and App_size information. App_typeIn2Type of frame within Buffer : 00 – control 01 – data Others – reserved App_ptrIn16Address pointer to location of data/control frames App_sizeIn16Size of data/control frames App_doneOut1Application processing done signal. Indicates that Application block has completed the processing request. System Control may assert a new request. Active High.

32. OCRP Architecture 32 Application – Buffer Interface Signal NameIn/OutWidthDescription Buf_addrOut16Buffer address bus. Buf_rdOut1Buffer read enable. Buf_dataIn32Buffer read data bus (should be one clock latency between assertion of buf_addr until buf_data is available).

33. OCRP Architecture 33 Application – DAC Interface Signal NameIn/OutWidthDescription Data_out_validOut1DAC Data valid Tx_data_iOut16DAC I signal Tx_data_qOut16DAC Q signal

34. OCRP Architecture 34 DAC Interface Interleaves the I and Q data from the app block and gives out tx_sync, tx_data to the DAC. No commands at this point.

35. OCRP Architecture 35 DAC Interface - Application IF (As defined in Application – DAC Interface) Signal NameIn/OutWidthDescription data_out_validIn1DAC Data valid tx_data_iIn16DAC I signal tx_data_qIn16DAC Q signal

36. OCRP Architecture 36 DAC Interface – FPGA Top IF Signal NameIn/OutWidthDescription dac_syncOut1Sync signal which allows 2 streams of data to be sent to the DAC (I and Q). By default tx_sync = 0 for I data tx_sync = 1 for Q data. This can be changed by programming the appropriate register. dac_dataOut14Data to the DAC

37. OCRP Architecture 37