1. CRKIT R5 Architecture rev 0.1 WINLAB – Rutgers University April 25, 2011 Khanh Le

2. R5 Architecture Summary Objective : migration of R4 to Zynq platform + support of new RF module (400MHz-4GHz tuning range) Zynq : Integrated dual-core ARM processor + peripherals e.g. GigE, USB, i2c, SPI, UART… What are the Hardware implications ? 1.Access to GigE port through AMBA AXI bus -> new Ethernet port module (ethernet framing by PS) 2.New RF ports e.g. DA/AD interface modules 3.New PCORE wrapper containing ARM processor and dual AXI busses 4.New AXI ipif modules for AXI bus interfacing : one for RMAP Processor, one for Ethernet port 5.Replace SPI with I2C interface. Current SPI is no longer needed (remove). I2C is provided by PS. 6.Potentially replace all R4 FIFOs and Block RAMs 7.New clock architecture What are the Software implications ? 1.Add DMA support for PS GigE -> PL Ethernet Port 2.Add DMA support for PL Ethernet Port -> PS GigE 3.Some changes to overall memory map due to dual AXI bus architecture 4.Changes to RF control due to I2C interface and new radio (refer to ADI reference design) APP design remains the same, only Xilinx IPs may need to be replaced due to tool revision updates Overall software remain the same, no Linux support for the initial phase. Once HW is stable, port Linux including VITA support. Target design methodology : mixed-language, C/SystemC, UVM Goal for DARPA Challenge : functional spectrum sensing APP (mid-august time frame)

3. Implications to R4 Architecture Modify access thru AXI bus Serial IO + ref. clock modifications SPI no longer applicable Replace with ARM core, contains dual AMBA AXI busses : AXI0 -> GbE, AXI1 -> Framework Replace PLB IPIF with AXI IPIF

4. Zynq System-on-Chip Overview Programmable Peripherals CPU Cores AXI Master/Slave Ports Programmable Logic (PL) Processor subsystem (PS) Refer to Xilinx user guide ug585-Zynq-7000-TRM.pdf for further details Fixed external IO pins

5. CRKIT Framework Integration PCORE AXI1 GbE RMAP Processor AXI0 0x4000_0000 0x7FFF_FFFF 0x8000_0000 0xBFFF_FFFF CRKIT AXI IPIF APP + PKT RF AXI0 – 32-bit, Master Port AXI1 – 32-bit, Master Port

6. PS IPIF data paths PS M PL SM SM system_processing_system7_0_wrapper (processor) system_axi_interconnect_0_wrapper (axi bus 0) system_axi_ext_slave_conn_0_wrapper (external connector 0) PL SM axi_ipif_slv (gbe) BUS2IP IP2BUS PCORE Bring internal AXI signals to top level M PL SM SM system_axi_interconnect_1_wrapper (axi bus 1) system_axi_ext_slave_conn_1_wrapper (external connector 1) PL SM axi_ipif_slv ( rmap processor) BUS2IP IP2BUS 0x4000_0000 0x7FFF_FFFF 0x8000_0000 0xBFFF_FFFF M_AXI_GP0 M_AXI_GP1

7. GbE GbE -> IP Data Path DP RAM DMA AXI SLAVE IPIF PKT CTL CMD FIFO Elastic Buffer AXI BUS 0 GbE block (R5) Skip ETH header, Prepend Ethertype field to payload Packet Processor (R4) 1. gbe dma transfer 2. Processor updates CMDs Complete ETH packet storage (circular buffer) Ethertype field + IP packet 0152931 ptr[15:0]size[13:0]- Fixed length buffer size allocation Jumbo frames not supported Processor Subsystem CRKIT Framework

8. R4 - host2app PCORE CMD FORMAT If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Forward ethernet payload if :  incoming MAC = dMAC  incoming MAC = Broadcast Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE Ethertype = 0x0800 - IPv4 0x0806 - ARP Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM. REPLACE

9. IP -> GbE Data Path

10. R4 - app2host VRT Receiver Lookup using PortID dMAC/Ethertype from IP Processor if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP) else Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP) endif Lookup using PortID if (V == 1) then Enable VITA formatting else Disable VITA formatting endif dMAC/Ethertype appended to IP/VITA data

11. Ethernet Control Flows

12. Clock architecture

13. Ethernet Port + DMA

14. APP -> GigE VRT Receiver Lookup using PortID dMAC/Ethertype from IP Processor if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP) else Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP) endif Lookup using PortID if (V == 1) then Enable VITA formatting else Disable VITA formatting endif dMAC/Ethertype appended to IP/VITA data

15. GigE -> APP PCORE CMD FORMAT If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Forward ethernet payload if :  incoming MAC = dMAC  incoming MAC = Broadcast Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE Ethertype = 0x0800 - IPv4 0x0806 - ARP Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.

16. DA Port

17. AD Port

18. Memory Map

19. R4 - app2host MMU To prefetch configuration settings at VITA emitter and IP Processor. Next prefetch can commence during current payload transfer drdy - data ready dreq - data request CMD FORMAT PortID: 0-3 - APP0-3 ports 4-15 – PCORE ports size : data size in bytes ptr : pointer to data in memory Use CMD_CNT as ACK to MEM_CTL/PCORE to indicate completion of data removal from MEM.

20. R4 - host2app PCORE CMD FORMAT If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Forward ethernet payload if :  incoming MAC = dMAC  incoming MAC = Broadcast Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE Ethertype = 0x0800 - IPv4 0x0806 - ARP Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.

21. R4 - PCORE PCORE – RMAP RD/WR IP Host -> PCORE (UDP-1001) IP PCORE -> Host (UDP-1001) Address Decoding RTYPE: 0x2000 – RMAP READ 0x2001 – RMAP WRITE RADDR: Register address RDATA: Register data

22. R4 - APP

23. R4 – Memory Map Upper 4 MSBs : 0x0-0x1 : PCORE 0x2 : CRKIT Others : Unused 0x0 : CMN 0x1 : ETH 0x2 : PKT 0x4-0xB : APP 0xC : DAC IF 0xD : ADC IF INT SPI, LED DCM/CLOCK CE

24. R4 – Interrupt Architecture INTCuPIPIF CMN INT ETH INT PKT INT APP INT SYS INT PCORECR