1. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Analog to Digital Converter

2. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Presentation Outline Introduction: Analog vs. Digital? Examples of ADC Applications Types of A/D Converters A/D Subsystem used in the microcontroller chip Examples of Analog to Digital Signal Conversion Successive Approximation ADC

3. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Analog Signals Analog signals – directly measurable quantities in terms of some other quantity Examples: Thermometer – mercury height rises as temperature rises Car Speedometer – Needle moves farther right as you accelerate Stereo – Volume increases as you turn the knob.

4. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Digital Signals Digital Signals – have only two states. For digital computers, we refer to binary states, 0 and 1. “1” can be on, “0” can be off. Examples: Light switch can be either on or off Door to a room is either open or closed

5. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Examples of A/D Applications Microphones - convert pressure waves in the air into varying electrical signals Strain Gages - resistance changes with applied strain Thermocouple - temperature measuring device converts thermal energy to electric energy Voltmeters Digital Multimeters

6. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Just what does an A/D converter DO? Converts analog signals into binary words

7. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Analog  Digital Conversion 2-Step Process: Quantizing - breaking down analog value is a set of finite states Encoding - assigning a digital word or number to each state and matching it to the input signal

8. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Step 1: Quantizing Example: You have 0-10V signals. Separate them into a set of discrete states with 1.25V increments. (How did we get 1.25V? See next slide…) Output States Discrete Voltage Ranges (V) 00.00-1.25 11.25-2.50 22.50-3.75 33.75-5.00 45.00-6.25 56.25-7.50 67.50-8.75 78.75-10.0

9. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Quantizing The number of possible states that the converter can output is: N=2 n where n is the number of bits in the AD converter Example: For a 3 bit A/D converter, N=2 3 =8. Analog quantization size: Q=(V max -V min )/N = (10V – 0V)/8 = 1.25V

10. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Encoding Here we assign the digital value (binary number) to each state for the computer to read. Output States Output Binary Equivalent 0000 1001 2010 3011 4100 5101 6110 7111

11. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Accuracy of A/D Conversion There are two ways to best improve accuracy of A/D conversion: increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal. increasing the sampling rate which increases the maximum frequency that can be measured.

12. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Resolution Resolution (number of discrete values the converter can produce) = Analog Quantization size (Q) (Q) = V range / 2 n, where V range is the range of analog voltages which can be represented limited by signal-to-noise ratio (should be around 6dB) In our previous example: Q = 1.25V, if we used a 2-bit converter, then the resolution would be 10/2^2 = 2.50V.

13. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Sampling Rate Frequency at which ADC evaluates analog signal. As we see in the second picture, evaluating the signal more often more accurately depicts the ADC signal.

14. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Aliasing Occurs when the input signal is changing much faster than the sample rate. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz (the aliased signal) sine wave. Nyquist Rule: Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.

15. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Overall Better Accuracy Increasing both the sampling rate and the resolution you can obtain better accuracy in your AD signals.

16. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 A/D Converter Types Converters –Flash ADC –Delta-Sigma ADC –Dual Slope (integrating) ADC –Successive Approximation ADC

17. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Flash ADC Consists of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which produces a binary output

18. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Flash ADC Circuit

19. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 How Flash Works As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs.

20. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ADC Output

21. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Flash Advantages Simplest in terms of operational theory Most efficient in terms of speed, very fast limited only in terms of comparator and gate propagation delays Disadvantages Lower resolution Expensive For each additional output bit, the number of comparators is doubled i.e. for 8 bits, 256 comparators needed

22. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Sigma Delta ADC Over sampled input signal goes to the integrator Output of integration is compared to GND Iterates to produce a serial bit stream Output is serial bit stream with # of 1’s proportional to V in

23. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Outputs of Delta Sigma

24. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Sigma-Delta Advantages High resolution No precision external components needed Disadvantages Slow due to oversampling

25. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Dual Slope Converter The sampled signal charges a capacitor for a fixed amount of time By integrating over time, noise integrates out of the conversion Then the ADC discharges the capacitor at a fixed rate with the counter counts the ADC’s output bits. A longer discharge time results in a higher count t V in t FIX t meas

26. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Dual Slope Converter Advantages Input signal is averaged Greater noise immunity than other ADC types High accuracy Disadvantages Slow High precision external components required to achieve accuracy

27. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation ADC A Successive Approximation Register (SAR) is added to the circuit Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the MSB and finishing at the LSB. The register monitors the comparators output to see if the binary count is greater or less than the analog signal input and adjusts the bits accordingly

28. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation ADC Circuit

29. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output

30. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation Advantages Capable of high speed and reliable Medium accuracy compared to other ADC types Good tradeoff between speed and cost Capable of outputting the binary number in serial (one bit at a time) format. Disadvantages Higher resolution successive approximation ADC’s will be slower Speed limited to ~5Msps

31. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 TypeSpeed (relative)Cost (relative) Dual SlopeSlowMed FlashVery FastHigh Successive AppoxMedium – FastLow Sigma-DeltaSlowLow ADC Types Comparison

32. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation Example 10 bit resolution or 0.0009765625V of Vref Vin=.6 volts Vref=1volts Find the digital value of Vin

33. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation MSB (bit 9) –Divided V ref by 2 –Compare V ref /2 with V in –If V in is greater than V ref /2, turn MSB on (1) –If V in is less than V ref /2, turn MSB off (0) –V in =0.6V and V=0.5 –Since V in >V, MSB = 1 (on)

34. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation Next Calculate MSB-1 (bit 8) –Compare V in =0.6 V to V=V ref /2 + V ref /4= 0.5+0.25 =0.75V –Since 0.6<0.75, MSB is turned off Calculate MSB-2 (bit 7) –Go back to the last voltage that caused it to be turned on (Bit 9) and add it to V ref /8, and compare with V in –Compare V in with (0.5+V ref /8)=0.625 –Since 0.6<0.625, MSB is turned off

35. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation Calculate the state of MSB-3 (bit 6) –Go to the last bit that caused it to be turned on (In this case MSB-1) and add it to V ref /16, and compare it to V in –Compare V in to V= 0.5 + V ref /16= 0.5625 –Since 0.6>0.5625, MSB-3=1 (turned on)

36. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Successive Approximation This process continues for all the remaining bits.

37. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Using the Analog to Digital Converter in the MC9S12C32

38. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interfaces to external signals via Port AD 10- or 8-bit Successive Approximation ADC

39. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 8 input channels Subsystem operation controlled by ADCTL2-5 Registers Results placed in ATDDR0-7

40. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Conversion Sequence Power on Wait 20 μs for ATD power to stabilize Sample Successive Approximation End Conversion time –8-bit: 12-26 ATD Clock Cycles –10-bit: 14-28 ATD Clock Cycles

41. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output StatesDiscretized Voltage Range Binary Coded Equivalent 00 - 19.5 mV $00 119.6 - 39.0 mV $01 239.1 - 58.5 mV $02 …… … 2554.98 - 5.0 V $FF MC9S12  8 bits  2 8 = 256 MC9S12 accepts 0 – 5V range Voltage Range = (V RH – V RL )/255 * State

42. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDCTL2 $0082 ADPU: ATD ON (1) or OFF (0) AFFC: ATD Flag clears automatically (1) or Must read status register to clear flag (0) AWAI: ATD off in wait mode (1) or on in wait mode (0) ETRIGLE: External trigger on edge (0) or level (1) ETRIGP: Controls polarity of ext. trigger Falling edge/low level (0) or rising edge/high level (1) ETRIGE: Enables (1) or disables (0) external trigger ASCIE: ATD Sequence Complete Interrupt Enable Bit - Enabled (1) or Disabled (0) ASCIF: ATD Sequence Complete Interrupt Flag - No ATD interrupt occurred (0) or ATD sequence complete interrupt pending (1)

43. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDCTL3 $0083 S8C,S4C,S2C,S1C: Set the number of Conversions per sequence FIFO: Conversion results are mapped to corresponding result registers (0) or result registers are used as a rotating First In First Out (FIFO) queue (1) FRZ1,FRZ0: Determine function of ATD system during Freeze mode

44. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDCTL4 $0084 SRES8: 8-bit (1) or 10-bit (0) resolution SMP1,SMP0: Determines length of second part of sample PRS4:0: ATD clock prescaler bits

45. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Prescaler determines ATD Clock frequency Derived from Bus Clock Frequency

46. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDCTL5 $0085 DJM: Left Justified (0) or Right Justified (1) data in result registers DSGN: Unsigned data in result registers (0) or signed data in result registers (left justification only) (1) SCAN: Single conversion (0) or continuous conversion sequence (1) MULT: Sample only one channel (0) or sample across multiple channels (1) CC,CB,CA: Determine the channel to be sampled if MULT=0 or the first channel to be sampled if MULT = 1

47. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Left Justified Data

48. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Right Justified Data

49. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

50. ME4447/6405 ATDSTAT0 $0086 SCF: Conversion Sequence not completed (0) or completed (1) ETORF: External Trigger Overrun Flag - No overrun has occurred (0) or overrun has occurred (1) FIFOR: FIFO Overrun Flag - No overrun has occurred (0) or overrun has occurred (1) CC2:0: Determine the result register that will contain the current conversion

51. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDSTAT1 $008B CCFX: Conversion number X has not yet completed (0) or has completed and the result is available in ATDDRX (1)

52. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ATDDIEN $008D IENX: Disable digital input on PTADX (0) or enable digital input on PTADX

53. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 PORTAD $008F PTADX: Contains digital input value for port AD pin X

54. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Example Write a program to configure the ATD system to perform one capture of an analog signal from Channel 0 with an 8-bit resolution

55. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ORG$1000 LDAA#$80;ADPU=1 STAAATDCTL2 Power on ATD Subsystem ATDCTL2EQU$0082 ATDCTL4EQU$0084 ATDCTL5EQU$0085 ATDDR1HEQU$0092 ATDSTAT1EQU$008B ORG$2000 ADRESULTRMB1 Delay for power to stabilize LDY#160;delay for 20  s DELAY DEY BNEDELAY LDAA#$01;SCAN=0,MULT=0,CC:CA=001 STAAATDCTL5;start conversion LDX#ATDSTAT1;check for complete flag BRCLR 0,X #$02 ;CCF1 is bit 1 LDAAATDDDR1H;read chan. 1 STAAADRESULT;store in result SWI Set ADCTL to start conversion Wait until conv. complete Read result LDAA#$85;SRES8=1, PRESCALER BITS = 00101 STAAATDCTL4 8-bit resolution, appropriate prescaler