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July 10, 2001 Status Report of the ROD Testing at BNL Kin Yip Activity update of the ROD system at BNL: DAQ-1 with trigger controller Data corruption testing.

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Presentation on theme: "July 10, 2001 Status Report of the ROD Testing at BNL Kin Yip Activity update of the ROD system at BNL: DAQ-1 with trigger controller Data corruption testing."— Presentation transcript:

1 July 10, 2001 Status Report of the ROD Testing at BNL Kin Yip Activity update of the ROD system at BNL: DAQ-1 with trigger controller Data corruption testing calibration etc.

2 July 10, 2001 DAQ at BNL, too Started from the setup of L. Moneta’s, and with additional help from M. Caprini, K. Serguei and R. Jones Quite a bit of work to install and set up in a non- CERN software environment (  slackware etc.) I have also tackled some synchronization problem which may hang the system occassionally, with help from K. Serguei et al. NEW(!): Trigger Controller, according to M. Caprini, the first controller to be used for calibration and trigger control. Demonstrated to people in Atlas week at BNL and US Atlas review 1

3 July 10, 2001 Two controllers in two different crates

4 July 10, 2001

5 Controlling trigger rate

6 July 10, 2001 Issues related to data integrity SDRAM: After a couple newer versions of OC FPGA firmware from Daniel, we can now write to ~8 Mbytes without data corruption EOE flag doesn’t seem to come up at trigger rate >11.1 kHz VME read errors at high trigger rate are still there 2 A recent and different kind of data corruption (eg. the error bits are wrong) If rebooted, the data read from the FEB through the optical link seemed to be OK for a little while and then went crazy again This probably didn’t happen so regularly before in the last several months

7 July 10, 2001 Issues related to data integrity (cont.) There is a jumper in the GLink Receiver card which be used to control the phase between the data and clock But adjusting the jumper position didn’t solve the problem After a lot of detective work, the problem is found to be due to the fact that the temperature at the back of the VME crate is too high Temperature  60 o C ( with poor A/C in the lab.) for the Glink chip There didn’t seem to have this problem in the winter GLink chips have malfunctioned such that the phase between the data and clock would shift  corrupted data (including wrong error codes) Solution : I put a small fan blowing air right towards the Glink receiver card Temperature drops and the phase doesn’t change any more, which one can see even in a scope ! 2

8 July 10, 2001 Thermometer Pulse from the trigger analyzer board

9 July 10, 2001 Calibration and miscellaneous Regularly using a calibration board (LAPP) to inject signals to FEB  ROD, as part of the data chain See the plot … Making a small board to veto trigger on “BUSY” Progress in (DSP) calibration codes in SMU, Texas Installed TI's code composer studio v1.20 (Windows) but couldn’t produce an “executable” to run DSP correctly Technology (software) transferred to Jose M. Castelo to set up the ROD for TileCal 3

10 July 10, 2001 Data seen from the ROD using 1 calibration channel Pulse from the trigger analyzer board

11 July 10, 2001 Plans … Further optimize the DAQ system and extend the trigger controller with more functionalities (?) To be really used for doing calibration with the read- out chain of the BNL LAr electronics mock-up Hope to have and use more sophisticated calibration codes in the DSP from SMU soon …


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