1. VLSI Design Methodologies
EE116B (Winter 2001): Lecture # 4

2. Reading for this Lecture
Chapter 11 of Rabaey’s book

3. Four Phases in Creating a Chip
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Lecture
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Lecture

4. The Design Problem Source: sematech97
A growing gap between design complexity and design productivity
[Adapted from Copyright 1996 UCB]

5. Profound Impact on the way VLSI is Designed
The old way: manual transistor twiddling
expert “layout designers”
entire chip hand-crafted
okay for small chips… but cannot design billion transistor chips in this fashion
The new way: using CAD tools at high level
tools do the grunge work…
high levels of abstractions
synthesis from a description of the behavior
libraries of reusable cores, modules, and cells
Chip design increasingly like object-oriented software design!
[Adapted from Copyright 1996 UCB]

6. Designing a VLSI Economic viability affected by design time
Design time affected by the efficiency of
concept  requirements  architecture  logic/memory  circuit  layout
Continuous trade-off between
performance (speed, area, power)
size of die (hence cost of die and packaging)
time of design (hence cost of engineering & schedule)
ease of test generation and testability

7. VLSI-design Tools & Methodologies
Goal is to reduce complexity, increase productivity, and increase chances of a working chip
Key is the use of Constraints and Abstractions
Constraints
help automate the procedure by simplifying the problem
Abstractions
collapse detail and arrive at a simpler problem to deal with
Different design methodologies
different types of constraints and trade-offs
choice driven by economics!

8. Design Domains Behavioral Structural Physical (geometrical)
what a system does
Structural
how entities are connected together to perform the behavior
Physical (geometrical)
how to build a structure that has the required connectivity to implement the prescribed behavior

9. Levels of Design Abstractions for Each Design Domain
Architectural
Algorithmic
Module or functional block
Logical
Switch
Circuit
Device
etc.

10. Design Abstraction Levels
[Adapted from Copyright 1996 UCB]

11. Design Methodology
Design process traverses iteratively between behavior, structure, and geometry abstractions
CAD tools providing more and more automation

12. A More Simplified Flow

13. Principles of Structured Design Techniques
Hierarchy
Regularity
Modularity
Locality

14. Hierarchy Divide and conquer Analogy with software
compose system from simpler widgets
Analogy with software
break large programs into threads and subroutines
Hierarchy can be there in all domains
behavior, structural, physical
The hierarchy in different domains may not correspond
e.g. a structural hierarchy may not map well to physical

15. Example of Structural Hierarchy

16. Example of Physical Hierarchy

17. Example of Structural Hierarchy

18. Example of Physical Hierarchy

19. Repartitioning Structural Hierarchy to Fit Physical Hierarchy

20. Regularity Hierarchy breaks a system into submodules
but this may not solve the complexity problem
there may not be any regularity in the subdivision
we just end up with a large # of different submodules
Regularity as a guide
subdivide into a set of similar building blocks
e.g. RAM composed of identical cells
Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible

21. Regularity (contd.) Regularity can be at all levels
circuit: use identically sized transistors
gate: similar gate structures
higher level: architectures with identical processors
Regularity helps in many ways
correct by construction
reuse of design
simplify verification of correctness

22. Circuit-level Regularity Example
A 2-1 Mux
D-type edge triggered flipflop
One-bit full add
All designed using inverter and tristate buffer

23. Modularity
Condition that submodules have “well-defined” functions and interfaces
in addition to regularity and hierarchy
‘Well-formed” modules allow their interaction with others to be “well-characterized”
Depends on the situation
e.g. in s/w a subroutine has a well-defined interface
argument list with typed variables
e.g. in IC a well-defined physical, structural, and behavioral interface
pin position, layer, size, signal type, electrical characteristics, logic function

24. Why Modularity?
Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined
Allows team design by a number of designers
Examples:
bad use: use of transmission gates as inputs
internal signals now depend on source impedance
bad use: use dynamic CMOS logic but fail to latch or register the inputs
timing of each module will have to be checked

25. Example of Poor Modularity

26. Locality Modularity provided “well-characterized” interfaces
internals of modules unimportant to exterior interface
internal details remain at the local level
a form of “information hiding”
reduces apparent complexity of the module
Locality ensures that connections are between neighboring modules, avoiding long-distance connections
Example: timing locality so that time critical operations are local
clock generation and distribution network
entire clock cycle for global signals to traverse chip
placement so that global wiring is minimized
Analogy with software
global variables are to be avoided

27. Parallels between H/W & S/W Design
Strong parallels in the way VLSIs are designed and the way complex software is
HDLs used to describe hardware systems in essence merge these two disciplines
software methods used to define hardware
Hardware-software Co-design
But, can’t ignore hardware aspects entirely
important since a physical chip is the end product

28. Typical VLSI Design Flow

29. Types of Tools Analysis and verification Implementation and synthesis
Testability techniques

30. Design Analysis and Verification
Accounts for largest fraction of design time
More efficient when done at higher levels of abstraction
select of correct analysis level can reduce verification time by orders of magnitude
Two approaches:
simulation: depends on choice of excitation
verification: extracts desired results directly from circuit description
[Adapted from Copyright 1996 UCB]

31. Simulation Approaches
Key distinction is how are data & time represented?
Circuit-level simulation (e.g. Spice)
Switch-level simulation (e.g. IRSIM)
transistors as switches with resistance
Gate-level (logic) simulation
now obsolete due to logic synthesis
Functional simulation (e.g. VHDL, Verilog)
primitives of arbitrary complexity
Behavioral simulation (e.g. VHDL)
only mimic I/O functionality
hardware delay loses its meaning

32. Digital Data as Analog Signals
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation). Impractical for large circuits
[Adapted from Copyright 1996 UCB]

33. Representing Data as Discrete Entity
Discretizing the data using
switching threshold
{0,1,X} representation of data
The linear switch model
of the inverter
[Adapted from Copyright 1996 UCB]

34. Discretizing Time Evaluate circuits only at “interesting” times
Event-driven simulation
evaluate gates only at a future time of interest
current time + gate delay
for more accuracy gate delay = function of load
still, events can happen at any time
Further simplification: unit-delay model
events only at multiples of a unit time
Even further simplification: zero-delay model
events at clock
a.k.a. clock or cycle based simulation

35. Circuit vs. Switch Level Simulation
[Adapted from Copyright 1996 UCB]

36. Structural Description of Accumulator
Design defined as composition of
register and full-adder cells (“netlist”)
Data represented as {0,1,Z}
Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog
[Adapted from Copyright 1996 UCB]

37. Behavioral Description of Accumulator
Design described as set of input-output
relations, regardless of chosen
implementation
Data described at higher abstraction
level (“integer”)
[Adapted from Copyright 1996 UCB]

38. Behavioral Simulation of Accumulator
Discrete time
Integer data
(Synopsys Waves display tool)
[Adapted from Copyright 1996 UCB]

39. Timing Verification Enumerates and rank orders critical timing paths
Critical path
Enumerates and rank
orders critical timing paths
No simulation needed!
(Synopsys-Epic Pathmill)
[Adapted from Copyright 1996 UCB]

40. Issues in Timing Verification
False Timing Paths
[Adapted from Copyright 1996 UCB]

41. Design Verification
Simulation only tells how circuit reacted to input excitation that was specified
Verification tools analyze design and find problems
Example:
electrical verification
transistor sizing for rise/fall time constraints
timing verification
find critical path
functional (formal) verification
compare circuit behavior against designer’s specification
proof that the two are “equivalent”, i.e. proof that the circuit will work
e.g. prove that two state machines are equivalent

42. Implementation Methodologies
[Adapted from Copyright 1996 UCB]

43. Economics of Implementation
Decision depends on
Non-recurring engineering cost
engineering design cost (personnel, support etc.)
prototype manufacturing cost
Production cost (Recurring cost)
wafer cost, processing cost
die per wafer
die yield per wafer, packaging yield, final test yield
Fixed costs
data sheets, cost of sales
Important to estimate design time and design cost
guide to select the design method

44. Choosing a Design Style

45. Custom Circuit Design When performance & design density important
High cost and long time-to-market
justified only if
high volumes
design will be reused (e.g. library cell)
cost no concern
due to CAD tools, custom design is minimal

46. Tools for Custom Design
Layout editor (e.g. Virtuoso)
Symbolic layout
relative positioning followed by compactor
Design rule checking
technology file, hierarchical DRC
Circuit extraction
schematic from layout
transistors, caps, resistances, inductances
Netlist comparison and netlist isomorphism
Back annotation from layout to schematic

47. Custom Design - Layout Editor
Magic Layout Editor
(UC Berkeley)
[Adapted from Copyright 1996 UCB]

48. Symbolic Layout Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program
Stick diagram of inverter
[Adapted from Copyright 1996 UCB]

49. Cell-based Design Methodology
Why? Shorter design time!
but, larger penalty
Array-based design (later) cuts process steps and reduces time even further…
Standard cell
library of logic gate (nand, and, or etc.)
design as a schematic or netlist of cells from library
layout is generated automatically in rows
design and composition of library is the main issue
what fanout to design for?
Alternative versions of cells with different drive

50. Standard Cell Libraries
Typically contain a few hundred cells
inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops
Each gate type can have multiple implementations to provide adequate driving capability for different fanouts
e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors
the chip designer can choose the proper size to achieve high circuit speed and layout density
Cells characterized for various metrics, such as
delay time vs. load capacitance
Circuit, timing, and fault simulation models
cell data for place-and-route
mask data
Cells designed such that they can be abutted to form rows

51. Standard Cell Based Design
Routing channel
requirements are
reduced by presence
of more interconnect
layers
[Adapted from Copyright 1996 UCB]

52. Standard Cell - Example
[Brodersen92]
[Adapted from Copyright 1996 UCB]

53. Standard Cell - Example
3-input NAND cell
(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies
[Adapted from Copyright 1996 UCB]

54. Automatic Cell Generation (Compiled Cells)
Random-logic layout
generated by CLEO
cell compiler (Digital)
[Adapted from Copyright 1996 UCB]

55. Module Generators Logic gate okay for random logic
But, inefficient for regular structures
e.g. carry chain capacitance in N-bit adder
Standard cells do not exploit regularity
Structured custom design
macrocell generators, e.g. memories, multipliers
interconnects by abutment in both dimensions
datapath compilers
abutment in one dimension, routing in the other
usually “parameterizable”

56. Datapath Compilers: Linear Placement
[Adapted from Copyright 1996 UCB]

57. Datapath Layout

58. Macrocell Design Methodology
Floorplan:
Defines overall
topology of design,
relative placement of
modules, and global
routes of busses,
supplies, and clocks
Interconnect Bus
Routing Channel
[Adapted from Copyright 1996 UCB]

59. Channel Routing

60. Macrocell-based Design Example
SRAM
SRAM
Data paths
Routing Channel
Standard cells
Video-encoder chip
[Brodersen92]
[Adapted from Copyright 1996 UCB]

61. Array-based Design Cuts process steps and reduces time even further…
Several types:
Mask programmable arrays
pre-diffused so that several masks are eliminated
typically, only top metalization needs to be done
standard packages to keep packaging cost low
e.g. gate array, sea of gates
Pre-wired arrays
avoid detailed manufacturing totally
analogy with memory

62. Processing Steps in Gate Array Implementations

63. Gate Array - Sea-of-gates
Uncommited
Cell
Committed
Cell (4-input NOR)
[Adapted from Copyright 1996 UCB]

64. Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation
[Adapted from Copyright 1996 UCB]

65. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K
(0.6 mm CMOS)
[Adapted from Copyright 1996 UCB]

66. Pre-wired Arrays
Categories of pre-wired arrays (or, field programmable gate arrays)
fuse based (program once)
non-volatile EPROM or EEROM based
RAM based
[Adapted from Copyright 1996 UCB]

67. Programmable Logic Devices
PAL
PLA
PROM
[Adapted from Copyright 1996 UCB]

68. EPLD Block Diagram Macrocell Primary inputs Courtesy Altera Corp.
[Adapted from Copyright 1996 UCB]

69. Antifuse Normally high resistance (> 100 M)
on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure ( )

70. Antifuse-based Actel FPGAs
Standard-cell like
floorplan
[Adapted from Copyright 1996 UCB]

71. Detailed Interconnect
Programming interconnect using anti-fuses
[Adapted from Copyright 1996 UCB]

72. Basic Block in Actel FPGA

73. RAM-based FPGAs
[Adapted from Copyright 1996 UCB]

74. Basic Block (CLB) in RAM-based FPGAs
Courtesy of Xilinx
[Adapted from Copyright 1996 UCB]

75. RAM-based FPGA Xilinx XC4025
[Adapted from Copyright 1996 UCB]

76. General Architecture of Xilinx FPGAs

77. Switch Matrices & Interconnection between CLBs

78. XC2000 CLB of the Xilinx FPGA

79. Overview of VLSI Design Styles

80. Design synthesis
Behavior  Structure

81. Taxonomy of Synthesis Tasks
[Adapted from Copyright 1996 UCB]

82. Circuit Synthesis Logic equations  transistor schematics
selection of circuit style
complementary static, pass-transistor, dynamic etc.
construction of logic network
e.g. Euler path techniques
Transistor sizing
to meet performance constraints
major impact on area, power, timing
subtle process… sensitive to parasitics
usually circuit modeled by equivalent RC circuit
detailed knowledge of subsequent layout process needed for estimation of parasitic capacitances

83. RTL or Logic Synthesis
Generate structural view of a logic level network
Many ways of specifying:
FSMs, schematics, boolean equations, HDL etc.
Two step process:
technology independent phase
logic optimized using boolean & algebraic manipulation
technology mapping phase

84. Evolution of RTL Synthesis
2-Level logic minimization
Espresso from Berkeley
Suited for PLAs & PALs which were used a lot in 80s
Sequential and state-machine synthesis
state minimization, state encoding
Multilevel logic synthesis
Mis-II from Berkeley
standard-cell and FPGA
Full blown RTL synthesis from HDL
e.g. Synopsys’s VHDL compiler, Berkeley’s SIS

85. Example: Multi-level Logic Synthesis
Adder:
S = (A  B)  Ci Co = A.B + A.Ci + B.Ci

86. Architecture Synthesis
Also called behavior or high-level synthesis
Generate architecture from task description
under constraints on area, speed, power etc.
Three phases
allocation: figures out busses, execution units etc.
assignment: binds behavior operations to hardware resources
scheduling: order of operations
Also, transformations that manipulate input behavior to obtain superior solution
pipelining, parallelization etc.

87. Example of Architecture Synthesis;

88. Alternative Solution

89. Design-Evaluation Space

90. Design-Evaluation Space for a Logic Function

91. Area, Latency, Cycle-time Design Evaluation Space

92. Another Example of Architecture Synthesis

93. Alternative Implementations