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ECE 555 Digital Circuits & Components ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1.

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Presentation on theme: "ECE 555 Digital Circuits & Components ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1."— Presentation transcript:

1 ECE 555 Digital Circuits & Components ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1

2 IMPLEMENTATION STRATEGY FOR DIGITAL ICS 2

3 ECE 555 Digital Circuits & Components Impact of Implementation Choices 3 Energy Efficiency (in MOPS/mW) Flexibility (or application scope) None Fully flexible Somewhat flexible Hardwired custom Configurable/Parameterizable Domain-specific processor (e.g. DSP) Embedded microprocessor

4 ECE 555 Digital Circuits & Components Implementation Choices 4 Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches

5 ECE 555 Digital Circuits & Components The Custom Approach 5 Intel 4004 Courtesy Intel

6 ECE 555 Digital Circuits & Components Transition to Automation and Regular Structures 6 Intel 4004 (71) Intel 8080 Intel 8085 Intel 8286 Intel 8486 Courtesy Intel

7 ECE 555 Digital Circuits & Components Cell-based Design (or standard cells) 7 Routing channel requirements are reduced by presence of more interconnect layers

8 ECE 555 Digital Circuits & Components Standard Cell Example 8 [Brodersen92]

9 ECE 555 Digital Circuits & Components Standard Cell – The New Generation 9 Cell-structure hidden under interconnect layers

10 ECE 555 Digital Circuits & Components Standard Cell - Example 10 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

11 ECE 555 Digital Circuits & Components Automatic Cell Generations 11 Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell

12 ECE 555 Digital Circuits & Components A Historical Perspective: the PLA 12 x 0 x 1 x 2 AND plane x 0 x 1 x 2 Product terms OR plane f 0 f 1

13 ECE 555 Digital Circuits & Components Two-Level Logic 13 Inverting format (NOR- NOR) more effective Every logic function can be expressed in sum-of-products format (AND-OR) minterm

14 ECE 555 Digital Circuits & Components PLA Schematics (Logic-level) 14

15 ECE 555 Digital Circuits & Components PLA Schematic (Transistor-level) 15

16 ECE 555 Digital Circuits & Components PLA Layout – Exploiting Regularity 16

17 ECE 555 Digital Circuits & Components Breathing Some New Life in PLAs River PLAs A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing. No placement and routing needed and output buffers and the input buffers of the next stage are shared. 17 Courtesy B. Brayton

18 ECE 555 Digital Circuits & Components Macro Modules (or 8192 bit) SRAM Generated by hard-macro module generator

19 ECE 555 Digital Circuits & Components Soft MacroModules 19

20 ECE 555 Digital Circuits & Components Intellectual Property 20 A Protocol Processor for Wireless

21 ECE 555 Digital Circuits & Components Semicustom Design Flow 21 HDL Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Capture Design Iteration

22 ECE 555 Digital Circuits & Components The Design Closure Problem 22 Iterative Removal of Timing Violations (white lines)

23 ECE 555 Digital Circuits & Components Integrating Synthesis w/ Physical Design 23 Physical Synthesis RTL(Timing) Constraints Place-and-Route Optimization Artwork Netlist with Place-and-Route Info Macromodules Fixed netlists

24 ECE 555 Digital Circuits & Components Late-Binding Implementation 24 Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based

25 ECE 555 Digital Circuits & Components Gate Array Sea-of-gates 25 Uncommited Cell Committed Cell (4-input NOR)

26 ECE 555 Digital Circuits & Components Sea-of-gate Primitive Cells 26 Using oxide-isolationUsing gate-isolation

27 ECE 555 Digital Circuits & Components Sea-of-gates 27 Random Logic Memory Subsystem LSI Logic LEA300K (0.6 m CMOS) Courtesy LSI Logic

28 ECE 555 Digital Circuits & Components The return of gate arrays? 28 metal-5 metal-6 Via-programmable cross-point programmable via Via programmable gate array (VPGA) [Pileggi02] Exploits regularity of interconnect

29 ECE 555 Digital Circuits & Components Prewired Arrays Classification of prewired arrays (or field- programmable devices): Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Style Array-Based Look-up Table Programmable Interconnect Style Channel-routing Mesh networks 29

30 ECE 555 Digital Circuits & Components Fuse-Based FPGA 30 antifuse polysiliconONO dielectric n + antifuse diffusion 2 l Open by default, closed by applying current pulse

31 ECE 555 Digital Circuits & Components Array-Based Programmable Logic 31 PLAPROMPAL O 1 O 2 O 3 Programmable AND array Programmable OR array O 1 O 2 O 3 Programmable AND array Fixed OR array Indicates programmable connection Indicates fixed connection

32 ECE 555 Digital Circuits & Components Programming a PROM 32 f 0 1X 2 X 1 X 0 f 1 NA : programmed node

33 ECE 555 Digital Circuits & Components More Complex PAL 33 From Smith97 i inputs, j minterms/macrocell, k macrocells

34 ECE 555 Digital Circuits & Components Programmable Logic Block 2-input mux 34 F A0 B S 1 Configuration ABSF= X1X 0Y1Y 0YXXY X0Y Y0X Y1XX 1 Y 10X 10Y 1111 X Y

35 ECE 555 Digital Circuits & Components Logic Cell of Actel Fuse-Based FPGA 35

36 ECE 555 Digital Circuits & Components Look-up Table Based Logic Cell 36

37 ECE 555 Digital Circuits & Components Array-Based Programmable Wiring 37 Input/output pinProgrammed interconnection Interconnect Point Horizontal tracks Vertical tracks Cell

38 ECE 555 Digital Circuits & Components Mesh-based Interconnect Network 38 Switch Box Connect Box Interconnect Point

39 ECE 555 Digital Circuits & Components Transistor Implementation of Mesh 39

40 ECE 555 Digital Circuits & Components RAM-based FPGA 40 Xilinx XC4000ex Courtesy Xilinx

41 ECE 555 Digital Circuits & Components Design at a Crossroad: System-on-a-Chip Embedded applications where cost, performance, and energy are the real issues! Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive DSP and control intensive Mixed-mode Mixed-mode Combines programmable and application-specific modules Combines programmable and application-specific modules Software plays crucial role Software plays crucial role 41 RAM 500 k Gates FPGA + 1 Gbit DRAM Preprocessing Multi- Spectral Imager C system +2 Gbit DRAM Recog- nition Analog 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS

42 BACKUP 42

43 ECE 555 Digital Circuits & Components Productivity ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity

44 ECE 555 Digital Circuits & Components A Simple Processor 44 MEMORY DATAPATH CONTROL INPUT/OUTPUT

45 ECE 555 Digital Circuits & Components A System-on-a-Chip: Example 45 Courtesy: Philips

46 ECE 555 Digital Circuits & Components Design Methodology Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps 46

47 ECE 555 Digital Circuits & Components PLA Layout – Exploiting Regularity 47 V DD GND And-Plane Or-Plane


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