1. NEMS Devices OPPORTUNITIES AND CHALLENGES
Adrian Ionescu
Nanolab, EPFL Switzerland

2. Goal of this talk…
Prove that energy efficient nanolectronics is a must for the future…
… and NEMS is a potential key enabling low power technology.

3. Switch made for performance…
Source: Heike Riel, IBM.

4. … not for energy efficiency
Power crisis in nanoelectronics
Leakage power dominates in advanced technology nodes.
VT scaling saturated by 60mV/dec limit, voltage scaling slowed.
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.01
0.1 1
Gate Length (μm)
Passive Power Density
Active Power Density
Source: B. Meyerson (IBM)
Semico Conf., January 2004
Power Density (W/cm2)

5. Today’s computing: energy/bit
What matters:
energy / computed bit
scaling
systemability
system level metrics prevail over device level
Integrated approach for energy/bit at system level:
Switch
Memory
Interconnects
Architecture
Embedded Software

6. Average subthreshold swingVG
@ VD=Vdd
(mV/decade)

7. Subthermal switches A fundamental issue? m less than 1
active gate devices:
NEM relay or NEMFET
negative capacitance
n less than (kT/q)ln10
# injection in the channel
Tunnel FETs
Impact Ionization MOS

8. Nano-Electro-Mechanical (NEM) Devices
NEM switch
NEM memory
NEM resonators

9. Electro-mechanical info processing
as a multi-state logic, with the logic states dictated by a spatial configuration of movable objects
as vibrational modes of mechanical elements, based upon waves.
as a sensed or transduced signal operation.

10. NEMS simulation and modeling
Source: G. Li et al, Urbana-Champaign.

11. NEM relay as subthermal switch
Advantages:
- zero Ioff (zero static power).
- abrupt transition between off and on states.
(Unwanted?) feature of NEM switch:
- hysteresis due to different values of pull-in, Vpi (off-on transition) and pull-out, Vpo (off-on transition) voltages.
Pull-in voltage:

12. MEMS process integration
For low cost & high performance, post-CMOS integration is desirable.
Thermal process budget is constrained for MEMS fabrication: surface micromachining is low T
Si Substrate
foundry CMOS
MEMS
Source: T.J. King.

13. Electro-mechanical design
3-terminal relay:
Stanford
4-terminal relay:
UC Berkeley
2-terminal relay:
EPFL

14. MEM logic relay Nice but large (10’s micrometer) size! Scalable?
Source: V. Pott, T.J. King, UC Berkeley.

15. Metal NW relays Nice, small size! Ioff excellent But voltage
large: > 10V
Scalable?
W. W. Jang et al, Appl. Phys. Lett., 92(10), , 2008.

16. Relay-based IC design CMOS to real logic mappping
100x less energy per half-adder
Relay technology
F. Chen et al, ICCAD 2008.

17. Comms: energy per useful bit
Energy / useful bit =
transmit energy + transmitted energy + receive energy
Role of MEMS/NEMS in
low power communications?
10 2m
~1000 less than SoA
= signal processing +
front-end
= signal processing +
front-end +
sleep (“scan”) mode
PHY, MAC, NETW

18. First MEMS memory
B. Halg, "On a micro-electro-mechanical nonvolatile memory cell", IEEE Transactions on Electron Devices, Vol. 37, Iss. 10, 1990.
thin micromachined
bridge elastically deformed:
two stable mechanical
states : “0” and “1”
MOS process: Si02 layer bridge covered by a 2nm thin Cr
state of the bridge changed using electrostatic forces
read out by sensing the capacitance
Size: ~hundreds mm2
Actuation voltage: > 40V

19. Bistable NEM NV memory cell
Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, H. Mizuta, S. Oda, "Nanoelectromechanical nonvolatile memory device incorporating nanocrystalline Si dots", Journal of Applied Physics, 100, 2006.

20. NEMORY cell concept (1) Nano-Electro-Mechanical NV memory
W.Y. Choi; H. Kam; D. Lee, J. Lai, T.-J. King Liu, "Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration", Technical Digest of IEEE International Electron Devices Meeting, IEDM 2007.
Nano-Electro-Mechanical NV memory
RWL as a top electrode
BL as a movable mechanical beam: information stored as BL position
ONO stack for charge storage
WWL as a lower electrode

21. NEMORY cell concept
NEMory cell operation is based on the hysteretic behavior of a mechanical gap-closing actuator.
Charge in the ONO layer is used to shift the hysteresis curves by Voffset, to achieve bistability at 0 V (VBL-WWL  VBL - VWWL), thus enabling non-volatile storage.

22. FinFACT –switch & memory
J.W. Han, Jae-Hyuk Ahn, Min-Wu Kim, Jun-Bo Yoon, and Yang-Kyu Choi, "Monolithic Integration of NEMS-CMOS with a Fin Flip-flop Actuated Channel Transistor (FinFACT)", IEDM 2009.
Principle: laterally movable (suspended) silicon FIN, bistable & sensed by transistor current flow.

23. FinFACT (2)
Depending on design (width) can be used both as NV (ROM) or SRAM.
Trade-off between the endurance and retention.

24. CNT-based memory cell
J.E. Jang et al, "Nanoscale memory cell based on a nanoelectromechanical switched capacitor", Nature Nanotechnology, Vol. 3, Jan. 2008, pp
NEM switched capacitor structure based on vertically aligned MW CNTs
- Capacit. of CNT NEM DRAM cell (diameter=60 nm; length=1.6 mm; SiNx,=40 nm): value of 0.59 fF with available potential of 2.4 mV for bit line sensing in a conventional DRAM design.
15 fF and 60–80 mV (Gbit DRAM) possible by the integration of high-k (not shown)
voltages > 14V

25. NEMS memory figures of merit
comparable cell area
scalable/comparable operation voltages
lowest program/erase energy: sub J/bit.

26. NEM resonators Passive MEMS resonator Resonant body transistor
Probably the most promising family of RF M/NEMS.
Embedding full equivalent circuit functions (RLC) with very high-Q and voltage tuning (possible replacement of quartz).
Applications: oscillators, mixing, filtering, sensing.
Passive MEMS resonator
Resonant body transistor
Adrian Ionescu, GRC 2012 26

27. Their scaling… Frequency, mass, Q mass & force detection
Fully-depleted RB-FET:
0.5 µm x 0.25 µm x 10 µm
Nanowire RB-FET:
40 nm x 40 nm x 2 um
NW-FET body
Frequency, mass, Q
mass & force detection
nm SOI-CMOS technology
integration density, complexity
400 nm

28. Low power characteristics
Tunable operation point:
Trade-off: gain versus power.
Experiment: resonance from strong to weak inversion.
nW static power consumption in weak-inversion (PDC < PAC ).
S. T. Bartsch, A.M. Ionescu, IEDM 2010.

29. Vibrating body transistors
Double-gate (in-plane) VB-FET resonator: transistor detection improves output signal by more than +30dB.
Transistor
Capacitive
D. Grogg et al, IEDM 2008.

30. Full circuit functions…
Transistor-based homodyne / heterodyne mixing.
Mixing coupled to mechanical motion.
Signal-to-background improvement.
Applications: VHF mixer-filter, closed-loop configurations.
Mixer output [a.u.]
Frequency [MHz]
Gate Votlage[V]
Imix ~ gm
Cc-Beam: x 0.2 x 3 µm3
f0=78 MHz, Q=1100
S.T.Bartsch et al, ACS Nano 2011.

31. Ultra-scaled single-NEM radio
Highly sensitive integrated sensor arrays (~ attogram)
Ultra miniaturized single-device radios (RF front ends)

32. Vibrating body CNT FET Device concept: SW CNT instead of Si
fres ~100MHz-1GHz
strong piezores. Effect 2xf
DG, 100nm airgap
By resist-assisted DEP
(>107 CNTs/cm2)
A.M. Ionescu, IEDM 2011
Adrian Ionescu
Adrian Ionescu, GRC 2012 32 32 32

33. Nano-scale active mass balance
Source: Ji Cao, EPFL.

34. Summary (1) Energy efficient devices: a must for the future!
Challenges:
Relays
scaling of:
gaps & size
operation voltage
reliability of contacts & packaging
dedicated IC design
Resonators
analog/RF & sensing
NEMS

35. Summary (2)
NEM memory:
exploit the. electromechanical hysteresis of movable structures by a gap closing Storage layer: specific purpose for shifting the hysteresis (NEMory, Oda’s memory, SG-FET)!
excellent co-integration with silicon CMOS. Low temperature processing, BEOL (3D-) integration possible, low cost.
Low voltage operation possible, limits ~1V
Program/erase & read times: <10ns
energy efficiency: less than J/bit in NEMory & SBM.
Trade-off between endurance & retention in FIN-FACT.
Robust in high temperature and radiation environments.
CNT-based memory: immature
Promising for embedded memory applications

36. Roadmap of NEMS applications