1. Computer Buses
For many of you who have depopulated his/her breadboards, THANKS!
There are still some to be depopulated. Please don’t forget to do it this week, please.

2. Final Exam – Thur, Dec 11, 4:15-6:20
Logic, Flip Flops, Timing, Synchronous / Asynchronous Circuits, Memory Organization, Finite State Machines (FSM)
RISC / CISC Computers, MIPS Organization, MIPS Instructions, MIPS Addressing, MIPS Frames / Context Switching, MIPS Assembly/Machine Programming (will have MIPS card)
Hamming Code
Developing MIPS Datapaths, MIPS FSM Implementations, and Alternative Microprogramming
Midterm
Pipelining - implementing, forwarding, handling branches
Cache – Direct, Associative, Set Associative
Virtual memory – Organization, Page Faults, and Look Aside Buffer
IA Bundled Instructions /explicit parallel, predicated execution, control speculation, speculative data loading, software pipelining / unraveling loops (don’t expect you to know details of the IA-64)
I/O Devices & Buses – Magnetic Disks, Solid State Disks, Flash Memory, Optical Disks, Magnetic Tape
- Organization, Implementation, Interrupts, Bus Control, DMA
60% on material covered after the midterm

3. Basic I/O System Example
Processor
Cache
Memory - I/O Bus
I/O
Controller
Disk …
I/O
Controller
Disk …
Main
Memory

4. Computer Buses The bus is a critical component of the Computer:
They are shared components that provide the paths for all parts of the computer to communicate with each other
They can reduce the complexity of communications between computer components
They contain conduits for data, “addressing”, and timing/control
They need a protocol that all users use
They can provide an easy way to evolve a computer system – add components
They can be a serious bottleneck if not designed and used appropriately
As systems grow, they need to evolve hierarchically
They can be parallel or serial
They can have data widths larger than the computer word length

5. Types of Buses Processor-memory bus (maybe proprietary)
Short and high speed
Matched to the memory system to maximize the memory-processor bandwidth
Optimized for cache block transfers
Backplane bus (maybe industry standard)
The backplane is an interconnection structure within the chassis
Used as an intermediary bus connecting I/O busses to the processor-memory bus
I/O bus (industry standard, e.g., SCSI, PCI,USB, Firewire)
Usually is lengthy and slower
Needs to accommodate a wide range of I/O devices
Connects to the processor-memory bus or backplane bus
Buses are traditionally classified as one of 3 types: processor memory buses, I/O buses, or backplane buses. The processor memory bus is usually design specific while the I/O and backplane buses are often standard buses.
In general processor bus are short and high speed. It tries to match the memory system in order to maximize the memory-to-processor BW and is connected directly to the processor.
I/O bus usually is lengthy and slow because it has to match a wide range of I/O devices and it usually connects to the processor-memory bus or backplane bus.
Backplane bus receives its name because it was often built into the backplane of the computer--it is an interconnection structure within the chassis.
It is designed to allow processors, memory, and I/O devices to coexist on a single bus so it has the cost advantage of having only one single bus for all components.
+2 = 16 min. (X:56)

6. Bus Characteristics Data & Address lines Control lines
Control lines: Master initiates requests
Bus
Master
Bus
Slave
Data lines: Data can go either way
Data & Address lines
Data, addresses, and complex commands
Control lines
Signal requests and acknowledgments
Indicate what type of information is on the data lines
Bus transaction consists of
Master issuing the command (and address) – request
Slave receiving (or sending) the data – action
Defined by what the transaction does to memory
Input – inputs data from the I/O device to the memory
Output – outputs data from the memory to the I/O device
A bus generally contains a set of control lines and a set of data lines. The control lines are used to signal requests and acknowledgments and to indicate what type of information is on the data lines. The data lines carry information between the source and the destination. This information may consists of data, addresses, or complex commands.
A bus transaction includes two parts: (a) sending the address and (b) then receiving or sending the data.
The bus master is the one who starts the bus transaction by sending out the address. The slave is the one who responds to the master by either sending data to the master if the master asks for data. Or the slave may end up receiving data from the master if the master wants to send data.
In the simplest system, the processor is the one and ONLY one bus master and all bus requests must be controlled by the processor. The major drawback of this simple approach is that the processor needs to be involved in every bus transaction and can use up too many processor cycles.

7. Buses What are the Bus design considerations?
Accessibility
Speed
Reliability
Extensibility
Bottle necks
Noise (electrical)
Flexibility
Ease of Interfacing
Power
Sharability
Communication Protocol
Length
Should Buses distribute Power?

8. Computer Bus Buses are composed of three sets of lines
Not all devices will use all lines in each category

9. What does this improve?

10. What is gained here?

11. Where are the challenges here?

12. How about this one?

13. Selector and Multiplexor Channels

14. Parallel and Serial I/O

15. Daisy Chained “Bus”

16. USB Topology

17. Computer Bus Control lines include: Clock(s) Interrupt Support
R/W
etc.

18. Bus Communications Bus Protocols Asynchronous Synchronous
Memory Read / Writes ?
I/O Read Writes?
Peer communication – e.g. CPU to CPU
Are communications verified?
Is there error checking ?

19. Synchronous and Asynchronous Buses
Synchronous bus (e.g., processor-memory buses)
Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock
Advantage: involves very little logic and can run very fast
Disadvantages:
Every device communicating on the bus must use same clock rate
To avoid clock skew, they cannot be long if they are fast
Asynchronous bus (e.g., I/O buses)
It is not clocked, so requires a handshaking protocol and additional control lines (ReadReq, Ack, DataRdy)
Advantages:
Can accommodate a wide range of devices and device speeds
Can be lengthened without worrying about clock skew or synchronization problems
Disadvantage: slow(er)
There are substantial differences between the design requirements for the I/O buses and processor-memory buses and the backplane buses.
Consequently, there are two different schemes for communication on the bus: synchronous and asynchronous.
Synchronous bus includes a clock in the control lines and a fixed protocol for communication that is relative to the clock.
Since the protocol is fixed and everything happens with respect to the clock, it involves very logic and can run very fast. Most processor-memory buses fall into this category.
Synchronous buses have two major disadvantages: (1) every device on the bus must run at the same clock rate. (2) And if they are fast, they must be short to avoid clock skew problem.
By definition, an asynchronous bus is not clocked so it can accommodate a wide range of devices at different clock rates and can be lengthened without worrying about clock skew.
The draw back is that it can be slow and more complex because a handshaking protocol is needed to coordinate the transmission of data between the sender and receiver.
+2 = 28 min. (Y:08)

20. Synchronous Bus

21. Asynchronous Bus Handshaking Protocol
Output (read) data from memory to an I/O device
ReadReq
Data
Ack
DataRdy
addr
data 1 2 3 4 6 5 7
I/O device signals a request by raising ReadReq and putting the addr on the data lines
Memory sees ReadReq, reads addr from data lines, and raises Ack
I/O device sees Ack and releases the ReadReq and data lines
ReadReq: used to indicate a read request for memory. The address is put on the data lines at the same time.
DataRdy: used to indicate that the data word is now ready on the data lines. In an output transaction, the memory will assert this signal. In an input transaction, the I/O device will assert it.
Ack: used to acknowledge the ReadReq or the DataRdy signal of the other party.
The control signals ReadReq and DataRdy are asserted until the other party indicates that the control lines have been seen and the data lines have been read; This indication is made by asserting the Ack line - HANDSHAKING.
Memory sees ReadReq go low and drops Ack
When memory has data ready, it places it on data lines and raises DataRdy
I/O device sees DataRdy, reads the data from data lines, and raises Ack
Memory sees Ack, releases the data lines, and drops DataRdy
I/O device sees DataRdy go low and drops Ack

22. Asynchronous Bus

23. Physical Considerations
How are the various components connected?
Unidirectional / bidirectional
And /Or combinational circuits
Wired Or circuits
Tri-state

24. Or configuration: Normal Gate Output Stage:
Observe that the output is always driven High or low.
What happens if we connect two of these to the bus?

25. Wired OR Now any new device can just be connected to the bus anywhere.
If no device is pulling the bus line low, it is high A NOR function

26. Tri-State Now each device can either drive the line high,
drive it low, or
leave it open

27. Symbols
Buffer
Open Collector
Tri-State

28. Signal Considerations
What about signal integrity?
Fanout
What about noise?
Drivers
What about length limitations?
Bus termination

29. Characteristic Impedance
Terminated at Char Impedance Not Terminated at Char Impedance

30. Termination comparisons
Open Termination
Short Termination
Proper Termination

31. A Typical I/O System Interrupts Processor Cache Memory - I/O Bus Main
Controller
I/O
Controller
I/O
Controller
This is a more in-depth picture of the I/O system of a typical computer.
The I/O devices are shown here to be connected to the computer via I/O controllers that sit on the Memory I/O busses. We will talk about buses on Friday.
For now, notice that I/O system is inherently more irregular than the Processor and the Memory system because all the different devices (disk, graphics) that can attach to it.
So when one designs an I/O system, performance is still an important consideration.
But besides raw performance, one also has to think about expandability and resilience in the face of failure.
For example, one has to ask questions such as:
(a)[Expandability]: is there any easy way to connect another disk to the system?
(b) And if this I/O controller (network) fails, is it going to affect the rest of the network?
+2 = 7 min (X:47)
Graphics
Disk
Disk
Network

32. Interrupt Systems
Interrupt Systems Allow Devices to request I/O Service when THEY are ready
Process?
Device given “permission” to generate an Interrupt Request
Request an Interrupt of the present process (IF priority allows)
On Request Acknowledge, provide “Vector” of Service Routine
(just like a memory read)
CPU makes a context switch and begins the Service Routine
On completion of the service, a context switchback occurs
The original process continues where it left off

33. Bus Master A bus Master controls the bus
Reads
Writes
Interrupt Request / Acknowledge
Bus Master Request / Acknowledge
Why would there be multiple potential Bus Masters?
Multiple Processor Shared Systems
One Processor can use the bus while another is doing internal processing
To accommodate the replacement of a “bad” bus master
Sometimes there is a voting system to determine Bus Control
Allows I/O devices to talk to memory or another I/O Device without using the processor time

34. Bus Master How does a Bus Master System work?
A potential Bus Master can Request the Bus Control
On Acknowledgement / Grant the new Master Takes Control
When there is a timeout due to no bus activity
A Potential Bus Controller announces intention to take control
Unless there is an objection, it then takes Control
If there are multiple requests
There is an arbitration process to determine who takes control

35. DMA (Direct memory Access)
Is there some way to use the bus when the master is not using it?
Yes, its called a DMA
To use the Bus, a device must request to DMA
On Grant, the device can make multiple transfers and then give up the Bus. During this time the Bus Master doesn’t use the Bus (possibly goes to sleep)
How is it used?
Typically, a device, like a Disk, requests the right to DMA one word or a Block of Words to a memory “page”.
When granted, the Disk fills the Block – in a burst (while the Bus Master perhaps sleeps) or one word at a time when the bus is not busy.
When the Block has been transferred, the Device may likely Interrupt the CPU to report the transaction is completed.

36. Some DMA Configurations

37. The Need for Bus Arbitration
Multiple devices may need to use the bus at the same time so must have a way to arbitrate multiple requests
Bus arbitration schemes usually try to balance:
Bus priority – the highest priority device should be serviced first
Fairness – even the lowest priority device should never be completely locked out from the bus
Bus arbitration schemes can be divided into four classes
Daisy chain arbitration – see next slide
Centralized, parallel arbitration – see next-next slide
Distributed arbitration by self-selection – each device wanting the bus places a code indicating its identity on the bus
Distributed arbitration by collision detection – device uses the bus when its not busy and if a collision happens (because some other device also decides to use the bus) then the device tries again later (Ethernet)
A more aggressive approach is to allow multiple potential bus masters in the system.
With multiple potential bus masters, a mechanism is needed to decide which master gets to use the bus next. This decision process is called bus arbitration and this is how it works.
A potential bus master (which can be a device or the processor) wanting to use the bus first asserts the bus request line and it cannot start using the bus until the request is granted.
Once it finishes using the bus, it must tell the arbiter that it is done so the arbiter can allow other potential bus master to get onto the bus.
All bus arbitration schemes try to balance two factors: bus priority and fairness. Priority is self explanatory. Fairness means even the device with the lowest priority should never be completely locked out from the bus.
Bus arbitration schemes can be divided into four broad classes. In the fist one:
(a) Each device wanting the bus places a code indicating its identity on the bus.
(b) By examining the bus, the device can determine the highest priority device that has made a request and decide whether it can get on.
In the second scheme, each device independently requests the bus and collision will result in garbage on the bus if multiple request occurs simultaneously.
Each device will detect whether its request result in a collision and if it does, it will back off for an random period of time before trying again.
The Ethernet you use for your workstation uses this scheme.
We will talk about the 3rd and 4th schemes in the next two slides.
+3 = 38 min. (Y:18)

38. Daisy Chain Bus Arbitration
Device 1
Highest
Priority
Device 2
Device N
Lowest
Priority
Ack
Ack
Ack
Release
Bus
Arbiter
Request
wired-OR
Data/Addr
Advantage: simple
Disadvantages:
Cannot assure fairness – a low-priority device may be locked out indefinitely
Slower – the daisy chain grant signal limits the bus speed
The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority.
The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme.
The advantage of this scheme is simple. The disadvantages are:
(a) It cannot assure fairness. A low priority device may be locked out indefinitely.
(b) Also, the daisy chain grant line will limit the bus speed.
+1 = 39 min. (Y:19)

39. Centralized Parallel Arbitration
Device 1
Device 2
Device N
Request1
Request2
RequestN
Ack1
Bus
Arbiter
Ack2
AckN
Data/Addr
Advantages: flexible, can assure fairness
Disadvantages: more complicated arbiter hardware
Used in essentially all processor-memory buses and in high-speed I/O buses

40. Layering – Example: OSI Network Layers
International Standards Organization’s (ISO) Open Systems Interconnection (ISO) Model:
The Physical Layer describes the physical properties of the various communications media, as well as the electrical properties and interpretation of the exchanged signals.
Example: this layer defines the size of Ethernet coaxial cable, the type of BNC connector used, and the termination method.
The Data Link Layer describes the logical organization of data bits transmitted on a particular medium.
Example: this layer defines the framing, addressing and check-summing of Ethernet packets.
The Network Layer describes how a series of exchanges over various data links can deliver data between any two nodes in a network.
Example: this layer defines the addressing and routing structure of the Internet.
The Transport Layer describes the quality and nature of the data delivery.
Example: this layer defines if and how retransmissions will be used to ensure data delivery.
The Session Layer describes the organization of data sequences larger than the packets handled by lower layers.
Example: this layer describes how request and reply packets are paired in a remote procedure call.
The Presentation Layer describes the syntax of data being transferred.
Example: this layer describes how floating point numbers can be exchanged between hosts with different math formats.
The Application Layer describes how real work actually gets done.
Example: this layer would implement file system operations.

41. Simple Example OF 7 Layer OSI Model
Application Layer: Set of C Instructions, Set of Data
{I0 I1 I2 …. IN Do D1 D2 … Dm}
Presentation Layer: ASCII Coding
{ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}
Session Layer: What process at computer x is communicating with what process at computer y
{X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}}
Transport Layer: Guaranteed Transmission, sequentially numbered packets of 4096 bytes
{GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}
Network Layer: Path through Network
{N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}}
Data Link Layer: Serial 256 bytes per frame
{STRT T{N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}}CHKSM}
Physical Layer: 9600Baud, Coax cable - {Start {….}Parity Stop Stop}

42. Ethernet packet

43. Bob Metcalf’s Ethernet Concept - 1976