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2002-12-13 D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP Magnus Själander.

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Presentation on theme: "2002-12-13 D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP Magnus Själander."— Presentation transcript:

1 2002-12-13 D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP Magnus Själander

2 MO/EAB/RTN/D Magnus Själander 2002-12-132 Contents Double Data Rate Interfaces DDR SDRAM Architecture and Functionality DDR Memory Controller Data Resynchronization Floorplan and Place & Route Future Work Conclusion

3 MO/EAB/RTN/D Magnus Själander 2002-12-133 Double Data Rate Interfaces Advantages Time of Flight Clock Skew Pin Count Bandwidth Disadvantage Synchronization New Data Transmissions on rising and falling edge Data Strobe

4 MO/EAB/RTN/D Magnus Själander 2002-12-134 SDRAM Architecture Four Banks Row and Column Select Lines 1T Memory Cells Sense Amplifiers Global Data Path

5 MO/EAB/RTN/D Magnus Själander 2002-12-135 DDR SDRAM Architecture 2n-prefetch Delay Lock Loop

6 MO/EAB/RTN/D Magnus Själander 2002-12-136 DDR SDRAM Improvements Long Delay in Column Decode and Data Lines Added a Delay Lock Loop to Increase Clock Frequency

7 MO/EAB/RTN/D Magnus Själander 2002-12-137 DDR SDRAM Commands Same Commands as for Standard SDRAM READ WRITE ACTIVATE PRECHARGE REFRESH MRS (Mode Register Set) Added EMRS (Extended MRS)

8 MO/EAB/RTN/D Magnus Själander 2002-12-138 DDR SDRAM Memory Controller

9 MO/EAB/RTN/D Magnus Själander 2002-12-139 Core Memory Controller

10 MO/EAB/RTN/D Magnus Själander 2002-12-1310 AHB Interface

11 MO/EAB/RTN/D Magnus Själander 2002-12-1311 Arbiter

12 MO/EAB/RTN/D Magnus Själander 2002-12-1312 Capturing the Data Phase Shift the Data Strobe Resynchronize the Data

13 MO/EAB/RTN/D Magnus Själander 2002-12-1313 Phase Shift the Data Strobe Delay Lock Loop Inverter Delay PCB Line Delay Programmable Delay Line with Temperature Sensing

14 MO/EAB/RTN/D Magnus Själander 2002-12-1314 Synchronization of the Data One Flip-Flop for each Flank to Sample

15 MO/EAB/RTN/D Magnus Själander 2002-12-1315 Synchronization of the Data Continued

16 MO/EAB/RTN/D Magnus Själander 2002-12-1316 Synchronization of the Data Continued Simplified Phase Detector

17 MO/EAB/RTN/D Magnus Själander 2002-12-1317 Floorplan

18 MO/EAB/RTN/D Magnus Själander 2002-12-1318 Place & Route

19 MO/EAB/RTN/D Magnus Själander 2002-12-1319 Future Work Improved Refresh Handling Attempt to Reduce Initial Latency for Bursts Improved Buffer Handling

20 MO/EAB/RTN/D Magnus Själander 2002-12-1320 Conclusion Working Implementation Smaller Changes to Improve Performance Highlights Difficulties and Solutions

21 2002-12-13 Questions ?

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