1. Page 1EL/CCUT T.-C. Huang May 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/05/03

2. Page 2EL/CCUT T.-C. Huang May 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (III)

3. Page 3EL/CCUT T.-C. Huang May 2004 TCH CCUT Example for D-Algorithm Schneider’s Circuit, 1967 d d’ h i e e’ j k f f’ l m b c a n g 0 1 1 D-frontier:________________J-frontier:________________ g 1 1 0 ikmn 1 1 1 1 0 1

4. Page 4EL/CCUT T.-C. Huang May 2004 TCH CCUT Multiple-Path Sensitization Example: Schneider’s Circuit d d’ h i e e’ j k f f’ l m b c a n g

5. Page 5EL/CCUT T.-C. Huang May 2004 TCH CCUT Multiple-Path Sensitization Conceptual Graph For most cases, backtracking is seldom And even single path is sufficient.

6. Page 6EL/CCUT T.-C. Huang May 2004 TCH CCUT Single-Path Sensitization Conceptual Graph Breadth-First Searching → Depth First Searching Consider only further error propagation and ignore the other gates from D-frontier.

7. Page 7EL/CCUT T.-C. Huang May 2004 TCH CCUT Backtracing Direct Search/Mapping objective to PI assignment x x xx x x x Inversion parity p : 1 if the inversion number is odd, otherwise 0. No values are assigned during backtracing. Backtrace(k, v k ) { v←v k ; while(k not PI){ select an input j of k with value x; v← v ⊕ inversion(k); k← j;} return(k, v); }

8. Page 8EL/CCUT T.-C. Huang May 2004 TCH CCUT PODEM Path-Oriented Decision Making [Goel 1981] PODEM( ) { if(Error at PO) return(Success); if(test not possible) return(Failure); select an objective (k, v k ) from D-frontier; (j, v j ) = Backtrace(k, v k ); Imply (j, v j ); if(PODEM( )) return(Success); Imply(j, not v j ); if(PODEM( )) return(Success); Imply(j, x); return Failure; } No Need to Consistency Check J-Frontier Backward Impli- cation

9. Page 9EL/CCUT T.-C. Huang May 2004 TCH CCUT Note 1.The syllabus is a little changed due to the progress. 2.Note that many topics are skipped at least including Other ATPG algorithms and extentions. Other cost functions/heuristics for decision/selection. ATPG for other fault models, including bridging. Function tests based on a variety of models.

10. Page 10EL/CCUT T.-C. Huang May 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (I)

11. Page 11EL/CCUT T.-C. Huang May 2004 TCH CCUT Testability 1.Controllability: The ability (probability, time, or cost) to activate the fault. 2.Observability: The ability (probability, time, or cost) to detect the error response.

12. Page 12EL/CCUT T.-C. Huang May 2004 TCH CCUT Design for Testability DFT Design for Testability Untestable Design Testability≠100% Testable Design

13. Page 13EL/CCUT T.-C. Huang May 2004 TCH CCUT Usual Causes to Untestability in SSF Model 1.Combinational Circuits: Reconvergent Fanout and Self-masking Redundant Circuits 2.Sequential Circuits: Uncontrollable at PPI (Pseudo Primary Input) Unobservable at PPO (Pseudo Primary Output) FF

14. Page 14EL/CCUT T.-C. Huang May 2004 TCH CCUT Ad Hoc for Testability Techniques 1.Test Points 2.Initialization (Reset) 3.Monostable Multivibrators (1-shots) 4.Oscillators and Clocks 5.Counters/Shift Registers 6.Partitioning Large Circuits 7.Logical Redundancy 8.Breaking Global Feedback Paths 頭痛醫頭，腳痛醫腳

15. Page 15EL/CCUT T.-C. Huang May 2004 TCH CCUT Employing Test Points g gg jumper CP0 OP CP0 OP g CP1 g 0 1 OP

16. Page 16EL/CCUT T.-C. Huang May 2004 TCH CCUT Scan Methodology 1.Integrated Scan Serial Scan 1.Serial Integrated Scan Full (Serial Integrated) Scan Partial (Serial Integrated) Scan 2.Isolated Serial Scan Non-Serial Scan 2.Boundary Scan

17. Page 17EL/CCUT T.-C. Huang May 2004 TCH CCUT Huffman Model for a Typical Scan Circuit Single Clock, Synchronous, DFF-based QD QD QD QD Combinational Circuit PI: Primary Inputs PPI: Pseudo PI PO: Primary Outputs PPO: Pseudo PO Clk M L N M X Z Q y D Y NS: Next StatePS: Present State SiSi SoSo

18. Page 18EL/CCUT T.-C. Huang May 2004 TCH CCUT Basic Scan Cells MDFF, Multiplexed D-Flipflop D Q Din 1 Din 2 Din 3 Dout 1 Dout 2 Dout 3 0 1 0 1 D Q 0 1 TEST SCAN_IN SCAN_OUT Din 1 Din 2 Din 3 Dout 1 Dout 2 Dout 3 D Q 1

19. Page 19EL/CCUT T.-C. Huang May 2004 TCH CCUT Scan Cell Insertion in HDL module ckt(Clk, input, output); … leftmodule (Clk, D2, …); DFF D2(Clk, D1, Q2); rightmodules (Clk, Q2, …); … endmodule module scan_cell (TEST, Clk, Di, Do, Si, So); … mux (TEST, Di, Si, Mo); DFF (Clk, Mo, Do); assign So=Do; endmodule Module scan_ckt(TEST, Clk, input, output, Si, So); … assign Si2=So1; leftmodule (Clk, D1, …); scan_cell SC1(TEST, Clk, D1, Q1, Si2, So2); rightmodules (Clk, Q1, …); … assign So=Son; endmodule Test Synthesis

20. Page 20EL/CCUT T.-C. Huang May 2004 TCH CCUT Boundary Scan Basic Concept TDI TDO

21. Page 21EL/CCUT T.-C. Huang May 2004 TCH CCUT Boundary Scan Background 1.Joint Test Action Group (JTAG) Boundary Scan Standard, 1988 2.IEEE P1149.1 Testability Bus Standard (Proposal), 1989 3.Basic Structure: TAP (Test Access Port) Controller Registers: IR (Instruction Register) and BR (Bypass Register) Extra Pins: TMS (Test Mode Singal) TCK (Test Clock) TDI (Test Data Input) TDO (Test Data Output)

22. Page 22EL/CCUT T.-C. Huang May 2004 TCH CCUT Boundary Scan Chip Architecture for BS1149.1 Application Circuit TDI TDO IR TAPC TMS TCK BR probably with scan chains

23. Page 23EL/CCUT T.-C. Huang May 2004 TCH CCUT A Basic Boundary Scan Cell IN 0 1 DQDQ 0 1 OUT SCAN_OUT SCAN_IN Shift Clock Update Mode 0 Normal mode 1 1 Scan mode 0 Capture mode Update mode Can update PIs (capture POs) simultaneously for detecting delay response. Can be used both as input and output boundary scan cells.

24. Page 24EL/CCUT T.-C. Huang May 2004 TCH CCUT Basic Test Access Controller A Synchronous Finite State Machine with 2X8 States TestReset Start/Iddle 1 0 0 Meta-state for Data Operations 11 Meta-state for Instruction Operations 1 11111

25. Page 25EL/CCUT T.-C. Huang May 2004 TCH CCUT State Diagram of TAPC 1 0 0 TestReset Start/Iddle 1 SelectIR CaptureIR ShiftIR Exit1IR PauseIR Exit2IR UpdateIR 0 0 1 0 1 1 1 1010 1 SelectDR CaptureDR ShiftDR Exit1DR PauseDR Exit2DR UpdateDR 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0

26. Page 26EL/CCUT T.-C. Huang May 2004 TCH CCUT Boundary Scan Exercise with TI BS1.0 1.Exercise and trace some examples using TI Scan Educator 1.0 2.Write the basic TMS sequence for applying a pattern and detecting the result to a circuit under test (CUT) originally with 4 pins. Hint: Initialization, Scanning in 4 bits, Update, Capture, Scanning out 4 bits, Update.