1. CS.305 Computer Architecture The Processor: Datapath and Control Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, and from slides kindly made available by Dr Mary Jane Irwin, Penn State University.

2. The Processor: Datapath and ControlCS305_06/2 The Processor  The implementation of a processor determines:  the clock cycle time, and  the number of clock cycles per instruction (CPI)  The processor consists of:  datapath  control unit  The key principles used in creating a datapath and designing a control unit can be illustrated in implementations of the core MIPS instruction set:  the memory reference instructions load word ( lw ) and store word ( sw )  the arithmetic-logical instructions add, sub, and, or, and slt  the branch equal ( beq ) and jump ( j ) instructions

3. The Processor: Datapath and ControlCS305_06/3  Our implementation of the MIPS is simplified  memory-reference instructions: lw, sw  arithmetic-logical instructions: add, sub, and, or, slt  control flow instructions: beq, j  Generic implementation  use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC)  decode the instruction (and read registers)  execute the instruction  All instructions (except j ) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 Decode Exec

4. The Processor: Datapath and ControlCS305_06/4 Clocking Methodologies  The (edge-triggered) clocking methodology defines when signals can be read and when they are written  Typical execution  read contents of state elements  send values through combinational logic  write results to one or more state elements  Assumes state elements are written on every clock cycle; if not, need explicit write control signal  write occurs only when both the write control is asserted and the clock edge occurs

5. The Processor: Datapath and ControlCS305_06/5 Fetching Instructions  Fetching instructions involves  reading the instruction from the Instruction Memory  updating the PC to hold the address of the next instruction Read Address Instruction Memory Add PC 4  PC is updated every cycle, so it does not need an explicit write control signal  Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

6. The Processor: Datapath and ControlCS305_06/6 Decoding Instructions  Decoding instructions involves  sending the fetched instruction’s opcode and function field bits to the control unit Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit  reading two values from the Register File Register File addresses are contained in the instruction

7. The Processor: Datapath and ControlCS305_06/7 Executing R Format Operations  R format operations ( add, sub, slt, and, or )  perform the (op and funct) operation on values in rs and rt  store the result back into the Register File (into register rd) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite  The Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File 31252015105 0 R-typeoprsrtrdshamtfunct

8. The Processor: Datapath and ControlCS305_06/8 Executing Load and Store Operations  Load and store operations involves  compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction  store value (read from the Register File during decode) written to the Data Memory  load value, read from the Data Memory, written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

9. The Processor: Datapath and ControlCS305_06/9 Executing Branch Operations  Branch operations involves  compare the operands read from the Register File during decode for equality ( zero ALU output)  compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instruction. ALU control Shift left 2 Add 4 PC Branch target address Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero Sign Extend 1632 (to branch control logic)

10. The Processor: Datapath and ControlCS305_06/10 Executing Jump Operations  Jump operation involves  replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28

11. The Processor: Datapath and ControlCS305_06/11 Creating a Single Datapath from the Parts  Assemble the datapath segments and add control lines and multiplexors as needed  Single cycle design – fetch, decode and execute each instructions in one clock cycle  no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders)  multiplexors needed at the input of shared elements with control lines to do the selection  write signals to control writing to the Register File and Data Memory  Cycle time is determined by length of the longest path

12. The Processor: Datapath and ControlCS305_06/12 Fetch, R, and Memory Access Portions MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

13. The Processor: Datapath and ControlCS305_06/13 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Observations  op field always in bits 31-26  address of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register  address of register to be written is in one of two places – in rt (bits 20- 16) for lw; in rd (bits 15-11) for R-type instructions  offset for beq, lw, and sw always in bits 15-0 31250 J op26-bit address 312520151050 Roprsrtrdshamtfunct 312520150 Ioprsrt16-bit immediate

14. The Processor: Datapath and ControlCS305_06/14  The Control Unit (CU) takes inputs and generates  a write signal for each state element,  the selector control for each mux,  and the ALU control. Control Unit RegDst Branch MemRead MemToReg RegWrite ALUSrc ALUOp MemWrite Instruction [31-26] Control Unit

15. The Processor: Datapath and ControlCS305_06/15  Depending on the instruction class, the ALU will need to perform one of the five functions.  For loads and stores: the ALU is used to compute the memory address by addition.  For R-type instructions: the ALU needs to perform one of the five actions –AND, OR, subtract, add, set on less than depending on the value of the 6-bit funct field.  For branch equal: the ALU must perform a subtraction. ALU Functions - Recap

16. The Processor: Datapath and ControlCS305_06/16  The ALU has three control inputs. Only five of the possible eight input combinations are used for the subset of instructions currently considered: ALU Control InputFunction 000AND 001OR 010add 110subtract 111set on less than ALU Control Inputs

17. The Processor: Datapath and ControlCS305_06/17 ALU Control Unit  The 3-bit ALU control input is generated by a small control unit (CU) that has as input:  the function field and  a 2-bit control field - ALUOp.  ALUOp encodes:  add (00) for loads and stores  subtract (01) for beq  An operation determined by the function field (10).  This is summarised in the following table:

18. The Processor: Datapath and ControlCS305_06/18 Instruction opcode ALUop Instruction operation Funct field Desired ALU action ALU control input lw00 load word XXXXXX add 010 sw00 store word XXXXXX add 010 beq 01 branch equal XXXXXX subtract 110 R-type 10 add 100000 add 010 R-type 10 subtract 100010 subtract 110 R-type 10 AND 100100 and 000 R-type 10 OR 100101 or 001 R-type 10 set on less than 101010 set on less than 111 ALU Control Unit - Summary

19. The Processor: Datapath and ControlCS305_06/19 ALUOpFunct Field Operation ALUOp1ALUOp0F5F4F3F2F1F0 00XXXXXX010 X1XXXXXX110 1XXX0000010 1XXX0010110 1XXX0100000 1XXX0101001 1XXX1010111 There are several ways of mapping the 2-bit ALUOp field and the 6-bit funct field to the three ALU control bits. Since the full truth table has 256 entries we can minimise this by only considering the truth table entries for which the ALU control must have a specific value: Deriving the ALU Control Inputs

20. The Processor: Datapath and ControlCS305_06/20 The truth tables for the three ALU control lines ALUOpFunct Field Operation2 ALUOp1ALUOp0F5F4F3F2F1F0 X1XXXXXX1 1XXXXX1X1 The truth table of Operation2 = 1 ALUOpFunct Field Operation1 ALUOp1ALUOp0F5F4F3F2F1F0 0XXXXXXX1 XXXXX0XX1 The truth table of Operation1 = 1 ALUOpFunct Field Operation0 ALUOp1ALUOp0F5F4F3F2F1F0 1XXXXXX11 1XXX1XXX1 The truth table of Operation0 = 1

21. The Processor: Datapath and ControlCS305_06/21 ALU Control Logic The ALU control block generates the three ALU control bits based on the function code and ALUOp bits

22. The Processor: Datapath and ControlCS305_06/22 Control Signals Signal NameEffect when deasserted (0)Effect when asserted (1) RegDstWrite register number comes from rt field Write register number comes from the rd field RegWriteNoneWrite register is written with the value on the Write data input ALUSrc2nd ALU operand is the 2nd register file output - read data 2 The 2nd ALU input is the sign-extended lower 16 bits of the instruction PCSrcThe PC is replaced by output of adder that computes PC + 4 The PC is replaced by output of adder that computes the branch target MemReadNoneAddressed data memory contents are put on the Read data output MemWriteNoneAddressed memory contents are replaced by Write data input value MemToRegThe value fed to register Write data input comes from the ALU The value fed to register Write data input comes from the data memory In addition to the 2-bit ALUOp control signal, seven other single-bit control signals are required to control the simple datapath. These are:

23. The Processor: Datapath and ControlCS305_06/23 Control Signals  All but one of these control signals can be determined solely on the opcode field.  The PCSrc line is the exception as this signal should be set if the instruction is a branch and the Zero output of the ALU, which is used for equality comparison, is true.  To generate PCSrc we will need to AND together a signal from the control unit, which we will call Branch, with the Zero signal out of the ALU.  The following table determines how the control signals should be set for each opcode: InstructionRegDstALU Src MemTo Reg Reg Write Mem Read Mem Write BranchALUOp1ALUOp0 R-format 100100010 lw011110000 swX1X001000 beqX0X000101

24. The Processor: Datapath and ControlCS305_06/24 Operation of the Datapath  Before finalising the CU logic let's look at how each instruction uses the datapath.  Think of an instruction executing in a series of 'steps’  each 'step' focuses on the portion of datapath associated with it.  Remember that a single-cycle implementation is combinatorial and is not really a series of four distinct steps.  The datapath really operates in a single clock cycle, and the signals within the datapath can vary unpredictably during the clock cycle.

25. The Processor: Datapath and ControlCS305_06/25 R-type ‘steps’  There are four ‘steps’ to the execution of an R-type instruction such as add $rd,$rs,$rt 1.An instruction is fetched from the instruction memory and the PC is incremented. 2.Two registers, $rs and $rt, are read from the register file. 3.The ALU operates on the data read from the register file using the function code (bits 5-0 of the instruction) to generate the ALU function. 4.The result from the ALU is written into the register file using bits 15-11 of the instruction to select the destination register ($rd).

26. The Processor: Datapath and ControlCS305_06/26  There are five ‘steps’ in a load word such as lw $rt,offset($rs) 1.An instruction is fetched from the instruction memory and the PC is incremented. 2.A register, $rs, is read from the register file. 3.The ALU computes the sum of the value read from the register file and the sign-extended lower 16 bits of the instruction (offset). 4.The sum from the ALU is used as the address for the data memory. 5.The data from the memory unit is written into the register file using bits 20-16 of the instruction to select the destination register ($rt). Load ‘steps’

27. The Processor: Datapath and ControlCS305_06/27  There are four ‘steps’ to a branch instruction such as beq $rs,$rt,offset 1.An instruction is fetched from the instruction memory and the PC is incremented. 2.Two registers, $rs and $rt, are read from the register file. 3.The ALU performs a subtract on the data read from the register file. The value of PC + 4 is added to the sign-extended lower 16 bits of the instruction (offset) shifted left by two; the result is the branch target address. 4.The Zero result from the ALU is used to decide which adder result to store into the PC. Branch ‘steps’

28. The Processor: Datapath and ControlCS305_06/28  The control function can be defined simply as:  the outputs are the control lines  the input is the 6-bit opcode field Op[5-0]  Thus we can create a truth table for each of the outputs. Here's a recap on the encoding of the instructions of interest: Name Opcode in Decimal Opcode in binary Op5Op4Op3Op2Op1Op0 R-format0000000 lw35100011 sw43101011 beq4000100 Finalising the Control

29. The Processor: Datapath and ControlCS305_06/29 The control function for the simple single-cycle implementation is completely specified by the following truth table: Input or Output Signal NameR-formatlwswbeq Inputs Op50110 Op40000 Op30010 Op20001 Op10110 Op00110 Outputs RegDst10XX ALUSrc0110 MemToReg01XX RegWrite1100 MemRead0100 MemWrite0010 Branch0001 ALUOp11000 ALUOp00001 Finalising the Control

30. The Processor: Datapath and ControlCS305_06/30 Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

31. The Processor: Datapath and ControlCS305_06/31 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

32. The Processor: Datapath and ControlCS305_06/32 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

33. The Processor: Datapath and ControlCS305_06/33 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

34. The Processor: Datapath and ControlCS305_06/34 Instr[20-16] Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Control Unit Branch Instr [15-11] Instr[31-26]

35. The Processor: Datapath and ControlCS305_06/35 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

36. The Processor: Datapath and ControlCS305_06/36 Instr [15-11] Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr[31-26]

37. The Processor: Datapath and ControlCS305_06/37 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Control Unit Branch Instr [15-11] Instr[31-26]

38. The Processor: Datapath and ControlCS305_06/38 Instr[20-16] Instr[25-21] Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Control Unit Branch Instr [15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4 [31-28] 28 Jump Instr[31-26]

39. The Processor: Datapath and ControlCS305_06/39 Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction  especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  Is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

40. The Processor: Datapath and ControlCS305_06/40 Multicycle Datapath Approach  Let an instruction take more than 1 clock cycle to complete  Break up instructions into steps where each step takes a cycle while trying to balance the amount of work to be done in each step restrict each cycle to use only one major functional unit  Not every instruction takes the same number of clock cycles  In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result  only need one memory – but only one memory access per cycle  need only one ALU/adder – but only one ALU operation per cycle

41. The Processor: Datapath and ControlCS305_06/41  At the end of a cycle  Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) Multicycle Datapath Approach, con’t A, B – regfile read data registersALUout – ALU output register  Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory)

42. The Processor: Datapath and ControlCS305_06/42 The Multicycle Datapath with Control Signals

43. The Processor: Datapath and ControlCS305_06/43 Actions of the 1-bit Control Signals Signal nameEffect when deassertedEffect when asserted RegDstThe register file destination number for the Write register comes from the rt field. The register file destination number for the Write register comes from the rd field. RegWriteNone.The register selected by Write register number is written with the value on the Write data input. ALUSrcAThe first ALU operand is the PC.The first ALU operand comes from the register given by the rs field. MemReadNone.Memory content at the read address is put on Memory data output. MemWriteNone.Memory content at the write address is replaced by value on Write data input. MemToRegThe value fed to the register write data input comes from ALUOut. The value fed to the register file write data input comes from the MDR. IorDThe PC is used to supply the address to the memory unit. ALUOut is used to supply the address to the memory unit. IRWriteNone.The output of memory is written into IR. PCWriteNone.Source, as selected by PCSource, is written into PC. PCWriteCondNone.PC is written if Zero from ALU is asserted.

44. The Processor: Datapath and ControlCS305_06/44 Actions of the 2-bit Control Signals Signal nameValue (bin)Effect when asserted ALUOp00The ALU performs an add operation. 01The ALU performs a subtract operation. 10The function code field determines the ALU operation. ALUSrcB00The 2nd input to the ALU comes from the B register. 01The 2nd input to the ALU is the constant 4. 10The 2nd input to the ALU is the sign-extended lower 16 bits of the IR 11The 2nd input to the ALU is the sign-extended, lower 16 bits of the IR shifted left 2 bits. PCSource00Output of the ALU (PC + 4) is sent to the PC for writing. 01The contents of the ALUOut (the branch target address) are sent to the PC for writing. 10The jump target address (IR[25:0]) shifted left 2 bits and concatenated with PC + 4[31:28] is sent to the PC for writing.

45. The Processor: Datapath and ControlCS305_06/45  Multicycle datapath control signals are not determined solely by the bits in the instruction  e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next  Must use a finite state machine (FSM) for control  a set of states (current state stored in State Register)  next state function (determined by current state and the input)  output function (determined by current state and the input) Multicycle Control Unit Combinational control logic State Reg Inst Opcode Datapath control points Next State...

46. The Processor: Datapath and ControlCS305_06/46 Finite State Machine Diagrams

47. The Processor: Datapath and ControlCS305_06/47 Instruction Fetch and Decode FSM

48. The Processor: Datapath and ControlCS305_06/48 Memory-reference FSM

49. The Processor: Datapath and ControlCS305_06/49 R-type FSM

50. The Processor: Datapath and ControlCS305_06/50 Branch FSM

51. The Processor: Datapath and ControlCS305_06/51 Jump FSM

52. The Processor: Datapath and ControlCS305_06/52 Methods of Specifying/Implementing Control  Alternative methods for specifying and implementing control using some form of structured logic are shown below.  The arrows indicate possible design paths.

53. The Processor: Datapath and ControlCS305_06/53 The Five Steps of the Load Instruction  IFetch: Instruction Fetch and Update PC  Dec: Instruction Decode, Register Read, Sign Extend Offset  Exec: Execute R-type; Calculate Memory Address; Branch Comparison; Branch and Jump Completion  Mem: Memory Read; Memory Write Completion; R- type Completion (RegFile write)  WB: Memory Read Completion (RegFile write) Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5 IFetchDecExecMemWB lw INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

54. The Processor: Datapath and ControlCS305_06/54 Multicycle Advantages & Disadvantages  Uses the clock cycle efficiently – the clock cycle is timed to accommodate the slowest instruction step  Multicycle implementations allow functional units to be used more than once per instruction as long as they are used on different clock cycles but  Requires additional internal state registers, more muxes, and more complicated (FSM) control Clk Cycle 1 IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch R-type

55. The Processor: Datapath and ControlCS305_06/55 Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9 Cycle 10 IFetchDecExecMem lwsw IFetch R-type Clk Single Cycle Implementation: lwsw Waste Cycle 1Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to state register overhead

56. The Processor: Datapath and ControlCS305_06/56 Fallacies and Pitfalls  Pitfall: Microcode implementing a complex instruction may not be faster than a sequence using simpler instructions.  Microcode is usually only changed when new models of an architecture are released. Normal software can introduce of improvements in, say, algorithms at any time. The microcode sequence is also unlikely to be optimal for all possible combinations of operands.  Fallacy: If there is space in (the microcode) control store, new instructions are free of cost.  Because of upward compatibility is highly desirable, future models of an architecture will usually be forced to include these so-called free instructions.  Extra instructions may also be costly to implement in future technologies.  Additions incur the cost of longer development and test time plus the possibility of costs for repairing bugs in them after the hardware has shipped.