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CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure José Nelson Amaral.

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Presentation on theme: "CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure José Nelson Amaral."— Presentation transcript:

1 CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure José Nelson Amaral

2 CMPUT 229 - Computer Organization and Architecture I2 Reading Material Patt & Patel, Chapter 3

3 CMPUT 229 - Computer Organization and Architecture I3 The Light Switch

4 CMPUT 229 - Computer Organization and Architecture I4 A N-MOS transistor A Metal-Oxide Semiconductor (MOS) transistor has three terminals. The Gate controls the flow of electrons between the two other terminals. In a N-type MOS transistor, electrons will flow when a voltage of 2.9 V is applied to the Gate (closed circuit). If 0.0 V is applied to the Gate no electrons will flow (open circuit). 2.9 Volt battery (power supply) Gate

5 CMPUT 229 - Computer Organization and Architecture I5 The NOT Gate Problem: Use two MOS transistors to implement the following logic circuit: NOT 2.9 Volts 0 Volts In Out Your NOT circuit should implement the following logic function:

6 CMPUT 229 - Computer Organization and Architecture I6 P-MOS Transistor The operation of a P-type MOS transistor, is the opposite of an N-MOS: - electrons will flow when a voltage of 0.0 V is applied to the Gate (closed circuit). - If 2.9 V is applied to the Gate no electrons will flow (open circuit). Gate #1 #2

7 CMPUT 229 - Computer Organization and Architecture I7 2.9V 0V 0 Volts 2.9 Volts 0V 2.9 Volts 0 Volts 2.9V The NOT Gate In 2.9 Volts 0 Volts Out

8 CMPUT 229 - Computer Organization and Architecture I8 A= 0V B=0V The NOR Gate A C B C= 2.9V

9 CMPUT 229 - Computer Organization and Architecture I9 The NOR Gate A C B A= 0V C= 0V B=2.9V

10 CMPUT 229 - Computer Organization and Architecture I10 The NOR Gate A C B A= 2.9V C= 0V B= 0V

11 CMPUT 229 - Computer Organization and Architecture I11 The NOR Gate A C B A= 2.9V C= 0V B= 2.9V

12 CMPUT 229 - Computer Organization and Architecture I12 What Logic Function this Circuit Implements? A B C D This is an OR gate.

13 CMPUT 229 - Computer Organization and Architecture I13 The AND Gate A B C D

14 CMPUT 229 - Computer Organization and Architecture I14 Logic Functions INVERTER XX’ If X=0 then X’=1 If X=1 then X’=0 OR ABAB C=A+B If A=1 OR B=1 then C=1 otherwise C=0 ABAB C=A·B If A=1 AND B=1 then C=1 otherwise C=0 AND

15 CMPUT 229 - Computer Organization and Architecture I15 NOR and NAND Because these combination of gates are used often, there are special symbols to represent them: XYXY Z XYXY Z Z XYXY XYXY Z  

16 CMPUT 229 - Computer Organization and Architecture I16 First DeMorgan’s Law The complement of the OR is equal the AND of the complements. (X+Y)’ = X’Y’ XYXY Z Z Y X 

17 CMPUT 229 - Computer Organization and Architecture I17 Decoders yGeneral decoder structure yTypically n inputs, 2 n outputs y2-to-4, 3-to-8, 4-to-16, etc.

18 CMPUT 229 - Computer Organization and Architecture I18 Decoders 3-to-8 Line Decoder y 0 = a’b’c’ y 1 = a’b’c y 2 = a’bc’ y 3 = a’bc y 4 = ab’c’ y 5 = ab’c y 6 = abc’ y 7 = abc a b c

19 CMPUT 229 - Computer Organization and Architecture I19 Multiplexers 4-to-1 MUX I0I0 I1I1 I2I2 I3I3 AB Z ABI3ABI3 A B’ I 2 A’ B I 1 A’ B’ I 0 Z

20 CMPUT 229 - Computer Organization and Architecture I20 Adders zBasic building block is “full adder” y1-bit-wide adder, produces sum and carry outputs Cout is one if two or more of the inputs are one. S is one if an odd number of inputs are one.

21 CMPUT 229 - Computer Organization and Architecture I21 Full-adder circuit

22 CMPUT 229 - Computer Organization and Architecture I22 Ripple adder ySpeed limited by carry chain yFaster adders eliminate or limit carry chain x2-level AND-OR logic ==> 2 n product terms x3 or 4 levels of logic, carry lookahead

23 CMPUT 229 - Computer Organization and Architecture I23 A bi-stable circuit zHow to control it? yControl inputs zS-R latch

24 CMPUT 229 - Computer Organization and Architecture I24 D latch

25 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3DOUT2DOUT1DOUT0 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3DIN0DIN2DIN1 WE_L CS_L OE_L WR_L IOE_L 011011

26 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3 WE_L CS_L OE_L WR_L IOE_L 011011

27 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3 WE_L CS_L OE_L WR_L IOE_L 011011

28 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3 WE_L CS_L OE_L WR_L IOE_L 011011

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