1. Home Assignment 3 Logical Design Assigned. Deadline 2015 May 3 rd Sunday

2. Flip-Flops. Counters. Registers.  The D Latch  The D Flip-Flop  Flip-Flop Symbols  A Basic Digital Counter (ripple counter)  A Synchronous Binary Counter  A Synchronous Decimal Counter  Serial to Parallel Shift register  Parallel to Serial Shift register P&H Appendix-B Wakerly Ch.7

3. The D Latch Cannot experience a "race" condition caused by all inputs being at logic 1 simultaneously.

4. The D Flip- Flop

5. Flip-Flop Symbols

6. A Basic Digital Counter (ripple counter)

8. A Synchronous Binary Counter States Co un t DCBA 00000 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115

9. A Synchronous Decimal Counter States C ou nt DCBA 00000 00011 00102 00113 01004 01015 01106 01117 10008 10019

10. Serial to Parallel Shift register Parallel to Serial Shift register