1. FEMTO-JOULE SWITCHING Review of Low Energy Approaches for the Nano Era Jabulani Nyathi Washington State University Valeriu Beiu Washington State University Snorre, Aunet University of Oslo, Norway With credits to Joel Birnbaum (HP), Hugo De Man (IMEC/KUL), Kaushik Roy (Purdue), Mark Lundstrom (Purdue), Vojin G. Oklobdzija (UCDavis), Takayasu Sakurai (University of Tokyo), Tadahiro Kuroda (Keio University), Anantha Chandrakasan (MIT), Richard Brown (Univ. of Utah), and ITRS Roadmap

2. 2 Motivation

3. 3 Where are we going?

4. 4 How to get there? The very big picture 1960708090 2000 Year 2010 RT-ops FSM asp FPGA µC dspP µP ASIP Hardware ASIC IC Filters AD/DA RF memory gate opamp Softwar e Design Software embedded C Services OO cC++ Network VHDL IP System on Silicon Board

5. 5 How to get there? The very small picture 19902016 I D (on) I D (off) 0.00001  A 1000  A 10  A 10X increase per technology node 10 nm scale MOSFETs 1.2 nm

6. 6 As the electrons vanish

7. 7 Power Power Power

8. 8 The trend: power, V DD, and current Year Voltage [V] Power per chip [W] VDD current [A] 19982002200620102014 0 0.5 1 1.5 2 2.5 00 200500 Current Voltage Power

9. 9 How should we deal with power and speed? Device level devices must have low threshold voltages, reduced parasitic capacitances or better yet new devices Examples include fully and partially depleted silicon-on-insulator CMOS Novel nano devices (e.g., single electron transistors, molecular, spin transistor, etc.) Gate level Logic design styles that include Standard CMOS Domino logic Differential logic families Pseudo nMOS and many more Threshold logic Circuit level Clock gating, current sensing, etc Module level Will inherit the gains achieved at device, circuit and gate levels and manage these by employing innovative architectures (e.g., reduce switching activity). Chip level Asynchronous communication, optical interconnects

10. 10 Sources of power dissipation Power has been a secondary design issue to speed Device miniaturization and voltage scaling have led to: Fast switching speeds, High density designs, High leakage currents and ultimately increased power dissipation. In deep sub-micron (i.e. nano), the conflicting issues of high speed and low power are becoming even more prominent.

11. 11 Past techniques for power reduction Voltage/frequency scaling Limited by technology. Not possible below a certain feature-size. Architectural adaptation Shut off portions of core when not needed Dynamic speculation control Reconfigurable caches Limitations: Very few choices to make Only dynamic power being saved Has associated overhead

12. 12 TransMeta Example

13. 13 Expression for average power Sufficient details of the currents drawn must be studied to allow for a detailed power analysis. The average total power in digital CMOS circuits can be described by: P total = P dynamic + P short_circuit + P static The dynamic power component and methods to manage it, have seen a fair share of analysis.

14. 14 Power component expressions Each component of the average power can be analyzed further as follows: P dynamic = α V DD V swing C L f CLK With V DD being the supply voltage, V swing the output/internal node voltage swing, C L the load capacitance and f the switching rate of the output and α, the activity factor. P short_circuit = α I sc_ave V swing I sc_ave is the average short circuit current over a period. α is included because the short circuit currents occur only when the outputs switch.

15. 15 The static power … becomes important! The third component of the average power equation is: P static = P sub_leakage + P DC WhereP sub_leakage is due to sub-threshold leakage P DC is due to DC current For nano-electronics it is expected that the static component of power will be comparable to the dynamic power dissipation Standby power ( P sub_leakage ) – a component of static power will be the culprit due to scaling.

16. 16 Example: Reducing dynamic power P dynamic =  C L V DD V swing f CLK Reduce switching activity: Conditional clock Conditional precharge Switching-off inactive blocks Conditional execution Run it slower: Use parallelism Less pipeline stages Use double- edge flip-flop Technology scaling: The highest win Thresholds should scale Leakage starts to byte Dynamic voltage scaling Reducing the active load: Minimize the circuits Use more efficient design Charge recycling More efficient layout

17. 17 Is there an optimal design point ?

18. 18 Power dissipation and circuit delay Power : P= p t f CLK C L V DD +I 0 10 V DD 2 V th S (  =1.3) k C L V DD (V -V th )  Delay = kQ I = 1 2 3 4 -0.4 0 0.4 0.8 0 0.2 0.4 0.6 0.8 1 x 10 -4 th (V) V DD (V) Power (W) A B

19. 19 Power-delay product, energy-delay product Power-delay product is a misleading metric, as it favors a processor that operates at lower frequency Energy-delay is adequate, but energy delay 2 should be used instead Lowest Voltage – Highest Threshold – no optimum

20. 20 Energy-delay 2

21. 21 Lowering V DD to achieve ultra- low power Energy consumption is proportional to the square of V DD. Energy consumption is proportional to the square of V DD. V DD should be lowered to the minimum level which ensures the real-time operation. V DD should be lowered to the minimum level which ensures the real-time operation. Normalized workload 0.00.20.40.60.81.0 Normalized power 0.0 0.2 0.4 0.6 0.8 1.0 Variable V dd Fixed V dd

22. 22 Aggressively lowering V DD + V th If V DD and V th are dynamically scaled; the advantage is obvious

23. 23 The future: sub-threshold and body bias ?

24. 24 A fresh look at leakage currents Some device and circuit level techniques for leakage current reduction are: Dynamic threshold transistors (DTMOS) Technique permits the body voltage to be switched with the gate voltage. High threshold voltages in standby mode result in low leakage currents. Low threshold voltage in active mode allow for higher current drives (high speed). Multi-threshold CMOS (MTCMOS) A high threshold voltage device is placed in series with low threshold MOS devices Devices in the critical path are assigned low threshold voltages to allow for high gate speeds Devices that are not in the critical path are assigned high threshold voltages to dissipate minimum leakage power in standby mode. Digital sub-threshold voltage Devices operate in sub-threshold region (V gs < |V th |) Technique is suitable for ultra low power applications where speed is of secondary importance

25. 25 V out V in V DD DTMOS Inveter configuration Various DTMOS configurations DTMOS: Allows for control of the bulk terminal Good for low voltage operation (V DD < 0.6V)

26. 26 Low-V TH circuit (High leakage) High-V TH circuit (Low leakage) Critical paths Non-critical paths Basic MTCMOS architecture

27. 27 MTCMOS circuits configuration MTMOS: Low V th in active mode Power supply is disconnected through the high V th device in standby mode Extra high V th memory circuit needed if data retention is necessary in standby mode Low V t Devices or Logic High V t Device V sleep V DD V_HIGH V DD Low V t Devices or Logic High V t Device V sleep VGND

28. 28 Digital sub-threshold circuits Improved characteristics including higher gain, better noise margin, and more energy efficient Ratio-ed logic (pseudo/true-NMOS) compared to CMOS logic in terms of switching and power Pseudo NMOS: Switches faster Draws high currents (dc currents are dominant) Dissipates more power Both CMOS and pseudo-nMOS sub-threshold logic are easy to design and more efficient as compared to other known ultra-low power logic, such as energy-recovery logic

29. 29 Brown et al have compared floating body and DTMOS inverters. Body conditioning is expected to yield superior results Our ring oscillators use both conventional and adaptive body biasing. Ring oscillator configurations

30. 30 Ring oscillators @ different nodes (PDP) WpWp WnWn DelayCurrent SPEE D POWE RPDPEDP nm nsnA GAINnWfJfJ*ns 250 nm VDD (mV)450 CMOS3900 150 0296.90286 1.00267.64 2.2689 7 Pseudo nMOS1250 150 0183.00480 1.62437.90 1.4467 2 Pseudo + Swap1500 146.502800 2.0325236.91 5.4084 8 180 nm VDD (mV)450 CMOS3375 108 0176.70270 1.00244.30 0.7604 0 Pseudo nMOS900 108 075.50688 2.34624.67 0.3531 6 Pseudo + Swap1080 62.403055 2.8327517.15 1.0705 8 130 nm VDD (mV)300 CMOS4507804.302600 1.001560.67 0.0028 8 Pseudo nMOS4507802.505100 1.723060.76 0.0019 1 Pseudo + Swap4507802.405450 1.793270.78 0.0018 8

31. 31

32. 32 The best of both worlds ?

33. 33 Effect of using different circuits styles

34. 34 How are logic design styles affected?  CLCL V DD V swin g I sc *V DD I DC *V DD I sc *e -vt/vT *V DD Standard CMOS  3C L V DD 1.5 1X [0 if V DD ≤V tn +V tp ] 01 Domino  CLCL V DD 2 1X [0 if V DD ≤V tn +V tp ] 01 Pass Transistor  CLCL V DD V DD - V t 0.4001 Differential (standard)  2C L V DD 4 2X [0 if V DD ≤V tn +V tp ] 02 Differential w/ charge recycling  2C L V DD V DD /22 2X [0 if V DD ≤V tn +V tp ] 02 Pseudo nMOS  CLCL V DD V DD - V t 0.4 1X [0 if V DD ≤V tn ] 1X [0 if V DD ≤V] 1 P dynamic P short_circu it P DC P leakage LOGIC STYLE

35. 35 Instead of conclusions … Where is C L ? Silicon wafer Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 Metal 7

36. 36