1. Virtual Memory Topics Motivations for VM Address translation Accelerating translation with TLBs VM1 CS 105 “Tour of the Black Holes of Computing!”

2. – 2 – CS 105 Programs refer to virtual memory addresses movl (%ecx),%eax Conceptually very large array of bytes Each byte has its own address Actually implemented with hierarchy of different memory types System provides address space private to particular “process” Allocation: Compiler and run-time system Where different program objects should be stored All allocation within single virtual address space But why virtual memory? Why not physical memory? Virtual Memory (Previous Lectures) 00∙∙∙∙∙∙0 FF∙∙∙∙∙∙F

3. – 3 – CS 105 Problem 1: How Does Everything Fit? 64-bit addresses: 16 Exabyte Physical main memory: Few Gigabytes ? And there are many processes ….

4. – 4 – CS 105 Problem 2: Memory Management Physical main memory What goes where? stack heap.text.data … Process 1 Process 2 Process 3 … Process n x

5. – 5 – CS 105 Problem 3: How To Protect Processes Physical main memory Process i Process j Problem 4: How To Share? Physical main memory Process i Process j

6. – 6 – CS 105 Solution: Level Of Indirection Each process gets its own private memory space Solves the previous problems Physical memory Virtual memory Process 1 Process n mapping

7. – 7 – CS 105 Address Spaces Linear address space: Ordered set of contiguous non-negative integer addresses: {0, 1, 2, 3 … } Virtual address space: Set of N = 2 n virtual addresses {0, 1, 2, 3, …, N-1} Physical address space: Set of M = 2 m physical addresses {0, 1, 2, 3, …, M-1} Clean distinction between data (bytes) and their attributes (addresses) Each object can now have multiple addresses Every byte in main memory: one physical address, one (or more) virtual addresses

8. – 8 – CS 105 A System Using Physical Addressing Used in “simple” systems like embedded microcontrollers in devices like cars, elevators, and digital picture frames 0: 1: M-1: Main memory CPU 2: 3: 4: 5: 6: 7: Physical address (PA) Data word 8:...

9. – 9 – CS 105 Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory. Each process with its own address space Only “active” code and data is actually in memory – Working Sets Allocate more memory to process as needed. Provide Protection One process can’t interfere with another. because they operate in different address spaces. User process cannot access privileged information different sections of address spaces have different permissions.

10. – 10 – CS 105 A System Using Virtual Addressing Used in all modern desktops, laptops, workstations One of the great ideas in computer science MMU checks the cache 0: 1: M-1: Main memory MMU 2: 3: 4: 5: 6: 7: Physical address (PA) Data word 8:... CPU Virtual address (VA) CPU Chip

11. – 11 – CS 105 Why Virtual Memory (VM)? Efficient use of limited main memory (RAM) Use RAM as a cache for the parts of a virtual address space some non-cached parts stored on disk some (unallocated) non-cached parts stored nowhere Keep only active areas of virtual address space in memory transfer data back and forth as needed Simplifies memory management for programmers Each process gets the same full, private linear address space Isolates address spaces One process can’t interfere with another’s memory because they operate in different address spaces User process cannot access privileged information different sections of address spaces have different permissions

12. – 12 – CS 105 Motivation #1: DRAM a “Cache” for Disk Full address space is quite large: 32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes Disk storage was ~300X cheaper than DRAM storage 80 GB of DRAM: ~ $33,000 80 GB of disk: ~ $110 Still true: To access large amounts of data in a cost- effective manner, the bulk of the data must be stored on disk

13. – 13 – CS 105 DRAM Cache Organization DRAM cache organization driven by the enormous miss penalty DRAM is about 10x slower than SRAM Disk is about 10,000x slower than DRAM For first byte, faster for next byteConsequences Large page (block) size: typically 4-8 KB, sometimes 4 MB Fully associative Any VP (Virtual Page) can be placed in any PP (?) Requires a “large” mapping function – different from CPU caches Highly sophisticated, expensive replacement algorithms Too complicated and open-ended to be implemented in hardware Write-back rather than write-through

14. – 14 – CS 105 Memory Hierarchy: Core 2 Duo Disk Main Memory L2 unified cache L1 I-cache L1 D-cache CPU Reg 2 B/cycle8 B/cycle16 B/cycle1 B/30 cyclesThroughput: Latency:100 cycles14 cycles3 cyclesmillions ~4 MB 32 KB ~4 GB~500 GB Not drawn to scale L1/L2 cache: 64 B blocks Miss penalty (latency): 30x Miss penalty (latency): 10,000x

15. – 15 – CS 105 DRAM vs. SRAM as a “Cache” DRAM vs. disk is more extreme than SRAM vs. DRAM Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM Importance of exploiting spatial locality: First byte is ~100,000X slower than successive bytes on disk »vs. ~4X improvement for page-mode vs. regular accesses to DRAM Bottom line: Design decisions made for DRAM caches driven by enormous cost of misses DRAM SRAM Disk

16. – 16 – CS 105 Impact of Properties on Design If DRAM (Main Memory) was to be organized similar to an SRAM cache, how would we set the following design parameters? Line size? Large, since disk better at transferring large blocks Associativity? High, to minimize miss rate Write through or write back? Write back, since can’t afford to perform small writes to disk What would the impact of these choices be on: miss rate Extremely low. << 1% hit time Must match cache/DRAM performance miss latency Very high. ~20ms tag storage overhead Low, relative to block size

17. – 17 – CS 105 Locating an Object in a “Cache” SRAM Cache Tag stored with cache line Maps from cache block to memory blocks From cached to uncached form Save a few bits by only storing tag of data blocks in cache No tag for block not in cache Hardware retrieves information can quickly match against multiple tags X Object Name TagData D243 X 17 J105 0: 1: N-1: = X? “Cache”

18. – 18 – CS 105 Locating an Object in “Cache” Data 243 17 105 0: 1: N-1: X Object Name Location D: J: X: 1 0 On Disk “Cache”Page Table DRAM (Main Memory) Cache Each allocated page of virtual memory has entry in page table Page Table: Mapping from virtual pages to physical pages From cached form to uncached form Page table entry (tag) even if page not in memory Specifies disk address Only way to indicate where to find page OS retrieves information

19. – 19 – CS 105 A System with Virtual Memory Examples: workstations, servers, modern PCs, etc. Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table) CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses shared by OS and all processes

20. – 20 – CS 105 Page Faults (like “Cache Misses”) What if an object is on disk rather than in memory? Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory -VM and Multi-pgming are Symbiotic current process suspends, others can resume OS has full control over placement, etc. CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault

21. – 21 – CS 105 Servicing a Page Fault Processor Signals Controller Read block of length P starting at disk address X and store starting at memory address Y Read Occurs Direct Memory Access (DMA) Under control of I/O controller I / O Controller Signals Completion Interrupt processor OS resumes suspended process disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (2) DMA Transfer (1) Initiate Block Read (3) Read Done between read request & interrupt system is running other processes

22. – 22 – CS 105 Motivation #2: Memory Mgmt Multiple processes can reside in physical memory. How do we resolve address conflicts? what if two processes access something at the same address? kernel virtual memory Memory mapped region forshared libraries runtime heap (via malloc) program text (.text) initialized data (.data) uninitialized data (.bss) stack forbidden 0 %esp memory invisible to user code stack as a page the “brk” ptr Linux/x86 process memory image program text on a page

23. – 23 – CS 105 Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (e.g., read/only library code) Solution: Separate Virt. Addr. Spaces Virtual and physical address spaces divided into equal-sized blocks blocks are called “pages” (both virtual and physical) Each process has its own virtual address space operating system controls how virtual pages are assigned to physical memory... Virtual Address Space for Process 2: shared between processes

24. – 24 – CS 105 Contrast: Old Mac Mem Model MAC OS 1–9 Does not use traditional virtual memory All program objects accessed through “handles” Indirect reference through pointer table Objects stored in shared global address space P1 Pointer Table P2 Pointer Table Process P1 Process P2 Shared Address Space A B C D E “Handles” mem hole mgmt

25. – 25 – CS 105 Macintosh Memory Management Allocation / Deallocation Similar to free-list management of malloc/freeCompaction Can move any object and just update the (unique) pointer in pointer table “Handles” P1 Pointer Table P2 Pointer Table Process P1 Process P2 Shared Address Space A B C D E

26. – 26 – CS 105 Mac vs. VM-Based Memory Mgmt Allocating, deallocating, and moving memory: can be accomplished by both techniques Block sizes: Mac: variable-sized may be very small or very large VM: fixed-size size is equal to one page (4KB on x86 Linux systems) Allocating contiguous chunks of memory: Mac: contiguous allocation is required VM: can map contiguous range of virtual addresses to disjoint ranges of physical addressesProtection Mac: “wild write” by one process can corrupt another’s data

27. – 27 – CS 105 MAC OS X “Modern” Operating System Virtual memory with protection Preemptive multitasking Other versions of MAC OS require processes to voluntarily relinquish control Based on MACH OS Developed at CMU in late 1980’s

28. – 28 – CS 105 Motivation #3: Protection Page table entry contains access rights information hardware enforces this protection (trap into OS if violation occurs) Page Tables Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

29. – 29 – CS 105 VM Address Translation Virtual Address Space V = {0, 1, …, N – 1} Physical Address Space P = {0, 1, …, M – 1} M < N -- Usually… PDP 11/70 Address Translation MAP: V  P U {  } For virtual address a: MAP(a) = a’ if data at virtual address a is at physical address a’ in P MAP(a) =  if data at virtual address a is not in physical memory »Either invalid or stored on disk

30. – 30 – CS 105 VM Address Translation: Hit Processor Hardware Addr Trans Mechanism Main Memory a a' physical addressvirtual addresspart of the on-chip memory mgmt unit (MMU)

31. – 31 – CS 105 VM Address Translation: Miss Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  page fault physical address OS performs this transfer (only if miss) virtual addresspart of the on-chip memory mgmt unit (MMU)

32. – 32 – CS 105 virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Page offset bits don’t change as a result of translation VM Address Translation Parameters P = 2 p = page size (bytes). N = 2 n = Virtual address limit M = 2 m = Physical address limit M < N

33. – 33 – CS 105 Page Tables Memory resident page table (physical page or disk address) Physical Memory Disk Storage (swap file or regular file system file) Valid 1 1 1 1 1 1 1 0 0 0 Virtual Page Number ppn

34. – 34 – CS 105 Address Translation via Page Table virtual page number (VPN)page offset virtual address physical page number (PPN)page offset physical address 0p–1pm–1 n–10p–1p page table base register if valid=0 then page not in memory valid physical page number (PPN) access VPN acts as table index

35. – 35 – CS 105 Page Table Operation Translation Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)

36. – 36 – CS 105 Page Table Operation Computing Physical Address Page Table Entry (PTE)(Line) provides information about page if (valid bit = 1) then the page is in memory. »Use physical page number (PPN) to construct address if (valid bit = 0) then the page is on disk »Page fault

37. – 37 – CS 105 Page Table Operation Checking Protection Access rights field indicate allowable access e.g., read-only, read-write, execute-only typically support multiple protection modes (e.g., kernel vs. user) Protection violation fault if user doesn’t have necessary permission

38. – 38 – CS 105 CPU Trans- lation Cache Main Memory VAPA miss hit data Integrating VM and Cache Most Caches “Physically Addressed” Accessed by physical addresses Allows multiple processes to have blocks in cache at same time else Context Switch == Cache Flush Allows multiple processes to share pages Cache doesn’t need to be concerned with protection issues Access rights checked as part of address translation Perform Address Translation Before Cache Lookup But this could involve a memory access itself (of the PTE) Of course, page table entries can also become cached

39. – 39 – CS 105 CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss Speeding up Translation with a TLB “Translation Lookaside Buffer” (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries (PTE) for small number of pages

40. – 40 – CS 105 Address Translation with a TLB virtual address virtual page number page offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache...

41. – 41 – CS 105 Simple Memory System Example Addressing 14-bit virtual addresses 12-bit physical address Page size = 64 bytes 131211109876543210 11109876543210 VPO PPOPPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset) How Many V Pages: 2**? P Pages: 2**? Page Size/Bytes per page: 2**

42. – 42 – CS 105 Simple Memory System Page Table Only shows first 16 entries VPNPPNValidVPNPPNValid 0028108131 01–009171 023310A091 030210B–0 04–00C–0 051610D2D1 06–00E111 07–00F0D1

43. – 43 – CS 105 Simple Memory System TLB TLB 16 entries 4-way associative: bits 6 & 7 – set, bits 8..13 - Tag 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0 Line.....................

44. – 44 – CS 105 Simple Memory System Cache Cache 16 lines 4-byte line size Direct mapped: CT – Tag, CI- Set/Index, CO-Byte Position 11109876543210 PPOPPN CO CI CT IdxTagValidB0B1B2B3IdxTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140––––

45. – 45 – CS 105 Address Translation Example #1 Virtual Address 0x03D4 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

46. – 46 – CS 105 Address Translation Example #2 Virtual Address 0x0B8F VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

47. – 47 – CS 105 Address Translation Example #3 Virtual Address 0x0040 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

48. – 48 – CS 105 Multi-Level Page Tables Given: 4KB (2 12 ) page size 32-bit address space 4-byte PTEProblem: Would need a 4 MB page table! 2 20 *4 bytes Common solution multi-level page tables e.g., 2-level table (P6) Level 1 table: 1024 entries, each of which points to a Level 2 page table. Level 2 table: 1024 entries, each of which points to a page Level 1 Table... Level 2 Tables

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53. – 53 – CS 105 Views of Processes Programmer’s View Large “flat” address space Can allocate large blocks of contiguous addresses Process “owns” machine Has private address space Unaffected by behavior of other processes System View User virtual address space created by mapping to set of pages Need not be contiguous Allocated dynamically Enforce protection during address translation OS manages many processes simultaneously Continually switching among processes Especially when one must wait for resource »E.g., disk I/O to handle page fault

54. – 54 – CS 105 The End Definitions Page Table Working Set TLBProblems 3.13

55. – 55 – CS 105 Simplifying Linking and Loading Linking Each program has similar virtual address space Code, stack, and shared libraries always start at the same addressLoading execve() allocates virtual pages for.text and.data sections = creates PTEs marked as invalid The.text and.data sections are copied, page by page, on demand by the virtual memory system Kernel virtual memory Memory-mapped region for shared libraries Run-time heap (created by malloc ) User stack (created at runtime) Unused 0 %esp (stack pointer) Memory invisible to user code brk 0xc0000000 0x08048000 0x40000000 Read/write segment (. data,. bss ) Read-only segment (.init,. text,.rodata ) Loaded from the executable file

56. – 56 – CS 105 Address Translation Example #1 Virtual Address 0x03D4 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN _0FTLBI _3TLBT _03TLB Hit? YPage Fault? _NPPN: _0D_ Physical Address Offset _0_CI_5_CT _0D_Hit? YByte: __36 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

57. – 57 – CS 105 Address Translation Example #2 Virtual Address 0x0B8F VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

58. – 58 – CS 105 Address Translation Example #3 Virtual Address 0x0040 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT