1. – 1 – 15-213, F’02 Conventional DRAM Organization d x w DRAM: dw total bits organized as d supercells of size w bits cols rows 0 123 0 1 2 3 internal row buffer 16 x 8 DRAM chip addr data supercell (2,1) 2 bits / 8 bits / memory controller (to CPU)

2. – 2 – 15-213, F’02 Reading DRAM Supercell (2,1) Step 1(a): Row access strobe (RAS) selects row 2. cols rows RAS = 2 0 123 0 1 2 internal row buffer 16 x 8 DRAM chip 3 addr data 2/2/ 8/8/ memory controller Step 1(b): Row 2 copied from DRAM array to row buffer.

3. – 3 – 15-213, F’02 Reading DRAM Supercell (2,1) Step 2(a): Column access strobe (CAS) selects column 1. internal buffer cols rows 0 123 0 1 2 3 internal row buffer 16 x 8 DRAM chip CAS = 1 addr data 2/2/ 8/8/ memory controller Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. supercell (2,1) supercell (2,1) To CPU

4. – 4 – 15-213, F’02 Memory Modules : supercell (i,j) 64 MB memory module consisting of eight 8Mx8 DRAMs addr (row = i, col = j) Memory controller DRAM 7 DRAM 0 03178151623243263394047485556 64-bit doubleword at main memory address A bits 0-7 bits 8-15 bits 16-23 bits 24-31 bits 32-39 bits 40-47 bits 48-55 bits 56-63 64-bit doubleword 03178151623243263394047485556 64-bit doubleword at main memory address A

5. – 5 – 15-213, F’02 Typical Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. main memory I/O bridge bus interface ALU register file CPU chip system busmemory bus

6. – 6 – 15-213, F’02 Memory Read Transaction (1) CPU places address A on the memory bus. ALU register file bus interface A 0 A x main memory I/O bridge %eax Load operation: movl A, %eax

7. – 7 – 15-213, F’02 Memory Read Transaction (2) Main memory reads A from the memory bus, retreives word x, and places it on the bus. ALU register file bus interface x 0 A x main memory %eax I/O bridge Load operation: movl A, %eax

8. – 8 – 15-213, F’02 Memory Read Transaction (3) CPU read word x from the bus and copies it into register %eax. x ALU register file bus interface x main memory 0 A %eax I/O bridge Load operation: movl A, %eax

9. – 9 – 15-213, F’02 Memory Write Transaction (1) CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. y ALU register file bus interface A main memory 0 A %eax I/O bridge Store operation: movl %eax, A

10. – 10 – 15-213, F’02 Memory Write Transaction (2) CPU places data word y on the bus. CPU places data word y on the bus. y ALU register file bus interface y main memory 0 A %eax I/O bridge Store operation: movl %eax, A

11. – 11 – 15-213, F’02 Memory Write Transaction (3) Main memory read data word y from the bus and stores it at address A. Main memory read data word y from the bus and stores it at address A. y ALU register file bus interface y main memory 0 A %eax I/O bridge Store operation: movl %eax, A

12. – 12 – 15-213, F’02 Disk Geometry Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. spindle surface tracks track k sectors gaps

13. – 13 – 15-213, F’02 I/O Bus main memory I/O bridge bus interface ALU register file CPU chip system busmemory bus disk controller graphics adapter USB controller mousekeyboardmonitor disk I/O bus Expansion slots for other devices such as network adapters.

14. – 14 – 15-213, F’02 Reading a Disk Sector (1) main memory ALU register file CPU chip disk controller graphics adapter USB controller mousekeyboardmonitor disk I/O bus bus interface CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller.

15. – 15 – 15-213, F’02 Reading a Disk Sector (2) main memory ALU register file CPU chip disk controller graphics adapter USB controller mousekeyboardmonitor disk I/O bus bus interface Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory.

16. – 16 – 15-213, F’02 Reading a Disk Sector (3) main memory ALU register file CPU chip disk controller graphics adapter USB controller mousekeyboardmonitor disk I/O bus bus interface When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special “interrupt” pin on the CPU)

17. – 17 – 15-213, F’02 An Example Memory Hierarchy registers on-chip L1 cache (SRAM) main memory (DRAM) local secondary storage (local disks) Larger, slower, and cheaper (per byte) storage devices remote secondary storage (distributed file systems, Web servers) Local disks hold files retrieved from disks on remote network servers. Main memory holds disk blocks retrieved from local disks. off-chip L2 cache (SRAM) L1 cache holds cache lines retrieved from the L2 cache memory. CPU registers hold words retrieved from L1 cache. L2 cache holds cache lines retrieved from main memory. L0: L1: L2: L3: L4: L5: Smaller, faster, and costlier (per byte) storage devices

18. – 18 – 15-213, F’02 Caching in a Memory Hierarchy 0123 4567 891011 12131415 Larger, slower, cheaper storage device at level k+1 is partitioned into blocks. Data is copied between levels in block-sized transfer units 8 9143 Smaller, faster, more expensive device at level k caches a subset of the blocks from level k+1 Level k: Level k+1: 4 4 4 10

19. – 19 – 15-213, F’02 Request 14 Request 12 General Caching Concepts Program needs object d, which is stored in some block b. Cache hit Program finds b in the cache at level k. E.g., block 14. Cache miss b is not at level k, so level k cache must fetch it from level k+1. E.g., block 12. If level k cache is full, then some current block must be replaced (evicted). Which one is the “victim”? Placement policy: where can the new block go? E.g., b mod 4 Replacement policy: which block should be evicted? E.g., LRU 93 0123 4567 891011 12131415 Level k: Level k+1: 14 12 14 4* 12 0123 Request 12 4* 12

20. – 20 – 15-213, F’02 Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L1, then in L2, then in main memory. Typical bus structure: main memory I/O bridge bus interfaceL2 cache ALU register file CPU chip cache bussystem busmemory bus L1 cache

21. – 21 – 15-213, F’02 Inserting an L1 Cache Between the CPU and Main Memory a b c d block 10 p q r s block 21... w x y z block 30... The big slow main memory has room for many 4-word blocks. The small fast L1 cache has room for two 4-word blocks. The tiny, very fast CPU register file has room for four 4-byte words. The transfer unit between the cache and main memory is a 4-word block (16 bytes). The transfer unit between the CPU register file and the cache is a 4-byte block. line 0 line 1

22. – 22 – 15-213, F’02 General Org of a Cache Memory B–110 B–110 valid tag set 0: B = 2 b bytes per cache block E lines per set S = 2 s sets t tag bits per line 1 valid bit per line Cache size: C = B x E x S data bytes B–110 B–110 valid tag set 1: B–110 B–110 valid tag set S-1: Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data.

23. – 23 – 15-213, F’02 Addressing Caches t bitss bits b bits 0m-1 Address A: B–110 B–110 v v tag set 0: B–110 B–110 v v tag set 1: B–110 B–110 v v tag set S-1: The word at address A is in the cache if the tag bits in one of the lines in set match. The word contents begin at offset bytes from the beginning of the block.

24. – 24 – 15-213, F’02 Direct-Mapped Cache Simplest kind of cache Characterized by exactly one line per set. valid tag set 0: set 1: set S-1: E=1 lines per set cache block

25. – 25 – 15-213, F’02 Accessing Direct-Mapped Caches Set selection Use the set index bits to determine the set of interest. valid tag set 0: set 1: set S-1: t bitss bits 0 0 0 0 1 0m-1 b bits tagset indexblock offset selected set cache block

26. – 26 – 15-213, F’02 Accessing Direct-Mapped Caches Line matching and word selection Line matching: Find a valid line in the selected set with a matching tag Word selection: Then extract the word 1 t bitss bits 100i0110 0m-1 b bits tagset indexblock offset selected set (i): (3) If (1) and (2), then cache hit, and block offset selects starting byte. =1? (1) The valid bit must be set = ? (2) The tag bits in the cache line must match the tag bits in the address 0110 w3w3 w0w0 w1w1 w2w2 30127456

27. – 27 – 15-213, F’02 Direct-Mapped Cache Simulation M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads): 0 [0000 2 ], 1 [0001 2 ], 13 [1101 2 ], 8 [1000 2 ], 0 [0000 2 ] x t=1s=2b=1 xxx 10m[1] m[0] vtagdata 0 [0000 2 ] (miss) (1) 10m[1] m[0] vtagdata 11m[13] m[12] 13 [1101 2 ] (miss) (3) 11m[9] m[8] vtagdata 8 [1000 2 ] (miss) (4) 10m[1] m[0] vtagdata 11m[13] m[12] 0 [0000 2 ] (miss) (5) 0M[0-1]1 1M[12-13]1 1M[8-9]1 1M[12-13]1 0M[0-1]1 1M[12-13]1 0M[0-1]1

28. – 28 – 15-213, F’02 Why Use Middle Bits as Index? High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutive memory lines map to different cache lines Can hold C-byte region of address space in cache at one time 4-line Cache High-Order Bit Indexing Middle-Order Bit Indexing 00 01 10 11 00 0001 0010 0011 0100 01 0110 0111 1000 1001 10 1011 1100 1101 1110 11 00 0001 0010 0011 0100 01 0110 0111 1000 1001 10 1011 1100 1101 1110 11

29. – 29 – 15-213, F’02 Set Associative Caches Characterized by more than one line per set validtag set 0: E=2 lines per set set 1: set S-1: cache block validtagcache block validtagcache block validtagcache block validtagcache block validtagcache block

30. – 30 – 15-213, F’02 Accessing Set Associative Caches Set selection identical to direct-mapped cache valid tag set 0: valid tag set 1: valid tag set S-1: t bitss bits 0 0 0 0 1 0m-1 b bits tagset indexblock offset Selected set cache block

31. – 31 – 15-213, F’02 Accessing Set Associative Caches Line matching and word selection must compare the tag in each valid line in the selected set. 10110 w3w3 w0w0 w1w1 w2w2 11001 t bitss bits 100i0110 0m-1 b bits tagset indexblock offset selected set (i): =1? (1) The valid bit must be set. = ? (2) The tag bits in one of the cache lines must match the tag bits in the address (3) If (1) and (2), then cache hit, and block offset selects starting byte. 30127456

32. – 32 – 15-213, F’02 E=2, B=4, S=8. Words 0x0E34, 0x0DD5, 0x1FE4 And list memory address that will hit in Set 3. Set tag V B0 B1 B2 B3 tag V B0 B1 B2 B3 0 09 1 86 30 3F 10 00 0 -- -- -- -- 1 45 1 60 4F E0 23 38 1 00 BC 0B 37 2 EB 0 -- -- -- -- 0B 0 -- -- -- -- 3 06 0 -- -- -- -- 32 1 12 08 7B AD 4 C7 1 06 78 07 C5 05 1 40 67 C2 3B 5 71 1 0B DE 18 4B 6E 0 -- -- -- -- 6 91 1 A0 B7 26 2D F0 0 -- -- -- -- 7 46 0 -- -- -- -- DE 1 12 C0 88 37

33. – 33 – 15-213, F’02 Multi-Level Caches Options: separate data and instruction caches, or a unified cache size: speed: $/Mbyte: line size: 200 B 3 ns 8 B 8-64 KB 3 ns 32 B 128 MB DRAM 60 ns $1.50/MB 8 KB 30 GB 8 ms $0.05/MB larger, slower, cheaper Memory L1 d-cache Regs Unified L2 Cache Unified L2 Cache Processor 1-4MB SRAM 6 ns $100/MB 32 B L1 i-cache disk

34. – 34 – 15-213, F’02 Motivations for Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory. Each process with its own address space Only “active” code and data is actually in memory Allocate more memory to process as needed. Provide Protection One process can’t interfere with another. because they operate in different address spaces. User process cannot access privileged information different sections of address spaces have different permissions.

35. – 35 – 15-213, F’02 Motivation #1: DRAM a “Cache” for Disk Full address space is quite large: 32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes Disk storage is ~300X cheaper than DRAM storage 80 GB of DRAM: ~ $33,000 80 GB of disk: ~ $110 To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk 1GB: ~$200 80 GB: ~$110 4 MB: ~$500 Disk DRAM SRAM

36. – 36 – 15-213, F’02 Levels in Memory Hierarchy CPU regs CacheCache Memory disk size: speed: $/Mbyte: line size: 32 B 1 ns 8 B RegisterCacheMemoryDisk Memory 32 KB-4MB 2 ns $125/MB 32 B 1024 MB 30 ns $0.20/MB 4 KB 100 GB 8 ms $0.001/MB larger, slower, cheaper 8 B32 B4 KB cachevirtual memory

37. – 37 – 15-213, F’02 DRAM vs. SRAM as a “Cache” DRAM vs. disk is more extreme than SRAM vs. DRAM Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM Importance of exploiting spatial locality: First byte is ~100,000X slower than successive bytes on disk »vs. ~4X improvement for page-mode vs. regular accesses to DRAM Bottom line: Design decisions made for DRAM caches driven by enormous cost of misses DRAM SRAM Disk

38. – 38 – 15-213, F’02 Impact of Properties on Design If DRAM was to be organized similar to an SRAM cache, how would we set the following design parameters? Line size? Large, since disk better at transferring large blocks Associativity? High, to mimimize miss rate Write through or write back? Write back, since can’t afford to perform small writes to disk What would the impact of these choices be on: miss rate Extremely low. << 1% hit time Must match cache/DRAM performance miss latency Very high. ~20ms tag storage overhead Low, relative to block size

39. – 39 – 15-213, F’02 A System with Physical Memory Only Examples: most Cray machines, early PCs, nearly all embedded systems, etc. Addresses generated by the CPU correspond directly to bytes in physical memory CPU 0: 1: N-1: Memory Physical Addresses

40. – 40 – 15-213, F’02 A System with Virtual Memory Examples: workstations, servers, modern PCs, etc. Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table) CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses

41. – 41 – 15-213, F’02 Page Faults (like “Cache Misses”) What if an object is on disk rather than in memory? Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory current process suspends, others can resume OS has full control over placement, etc. CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault

42. – 42 – 15-213, F’02 Servicing a Page Fault Processor Signals Controller Read block of length P starting at disk address X and store starting at memory address Y Read Occurs Direct Memory Access (DMA) Under control of I/O controller I / O Controller Signals Completion Interrupt processor OS resumes suspended process disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (2) DMA Transfer (1) Initiate Block Read (3) Read Done

43. – 43 – 15-213, F’02 Motivation #2: Memory Management Multiple processes can reside in physical memory. How do we resolve address conflicts? what if two processes access something at the same address? kernel virtual memory Memory mapped region forshared libraries runtime heap (via malloc) program text (.text) initialized data (.data) uninitialized data (.bss) stack forbidden 0 %esp memory invisible to user code the “brk” ptr Linux/x86 process memory image

44. – 44 – 15-213, F’02 Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (e.g., read/only library code) Solution: Separate Virt. Addr. Spaces Virtual and physical address spaces divided into equal-sized blocks blocks are called “pages” (both virtual and physical) Each process has its own virtual address space operating system controls how virtual pages as assigned to physical memory... Virtual Address Space for Process 2:

45. – 45 – 15-213, F’02 Motivation #3: Protection Page table entry contains access rights information hardware enforces this protection (trap into OS if violation occurs) Page Tables Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

46. – 46 – 15-213, F’02 VM Address Translation Virtual Address Space V = {0, 1, …, N – 1} Physical Address Space P = {0, 1, …, M – 1} M < N Address Translation MAP: V  P U {  } For virtual address a: MAP(a) = a’ if data at virtual address a at physical address a’ in P MAP(a) =  if data at virtual address a not in physical memory »Either invalid or stored on disk

47. – 47 – 15-213, F’02 VM Address Translation: Hit Processor Hardware Addr Trans Mechanism Main Memory a a' physical addressvirtual addresspart of the on-chip memory mgmt unit (MMU)

48. – 48 – 15-213, F’02 VM Address Translation: Miss Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  page fault physical address OS performs this transfer (only if miss) virtual addresspart of the on-chip memory mgmt unit (MMU)

49. – 49 – 15-213, F’02 virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Page offset bits don’t change as a result of translation VM Address Translation Parameters P = 2 p = page size (bytes). N = 2 n = Virtual address limit M = 2 m = Physical address limit

50. – 50 – 15-213, F’02 Page Tables Memory resident page table (physical page or disk address) Physical Memory Disk Storage (swap file or regular file system file) Valid 1 1 1 1 1 1 1 0 0 0 Virtual Page Number

51. – 51 – 15-213, F’02 Address Translation via Page Table virtual page number (VPN)page offset virtual address physical page number (PPN)page offset physical address 0p–1pm–1 n–10p–1p page table base register if valid=0 then page not in memory valid physical page number (PPN) access VPN acts as table index

52. – 52 – 15-213, F’02 Page Table Operation Translation Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)

53. – 53 – 15-213, F’02 Page Table Operation Computing Physical Address Page Table Entry (PTE) provides information about page if (valid bit = 1) then the page is in memory. »Use physical page number (PPN) to construct address if (valid bit = 0) then the page is on disk »Page fault

54. – 54 – 15-213, F’02 Page Table Operation Checking Protection Access rights field indicate allowable access e.g., read-only, read-write, execute-only typically support multiple protection modes (e.g., kernel vs. user) Protection violation fault if user doesn’t have necessary permission

55. – 55 – 15-213, F’02 CPU Trans- lation Cache Main Memory VAPA miss hit data Integrating VM and Cache Most Caches “Physically Addressed” Accessed by physical addresses Allows multiple processes to have blocks in cache at same time Allows multiple processes to share pages Cache doesn’t need to be concerned with protection issues Access rights checked as part of address translation Perform Address Translation Before Cache Lookup But this could involve a memory access itself (of the PTE) Of course, page table entries can also become cached

56. – 56 – 15-213, F’02 CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss Speeding up Translation with a TLB “Translation Lookaside Buffer” (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages

57. – 57 – 15-213, F’02 Simple Memory System Page Table Only show first 16 entries VPNPPNValidVPNPPNValid 0028108131 01–009171 023310A091 030210B–0 04–00C–0 051610D2D1 06–00E111 07–00F0D1

58. – 58 – 15-213, F’02 Simple Memory System TLB TLB 16 entries 4-way associative 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0

59. – 59 – 15-213, F’02 Simple Memory System Example Addressing 14-bit virtual addresses 12-bit physical address Page size = 64 bytes 131211109876543210 11109876543210 VPO PPOPPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset)

60. – 60 – 15-213, F’02 Simple Memory System Cache Cache 16 lines 4-byte line size Direct mapped 11109876543210 PPOPPN CO CI CT IdxTagValidB0B1B2B3IdxTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140––––

61. – 61 – 15-213, F’02 Address Translation Example #1 Virtual Address 0x03D4 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

62. – 62 – 15-213, F’02 Address Translation Example #2 Virtual Address 0x0B8F VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

63. – 63 – 15-213, F’02 Address Translation Example #3 Virtual Address 0x0040 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address Offset ___CI___CT ____Hit? __Byte: ____ 131211109876543210 VPO VPN TLBI TLBT 11109876543210 PPOPPN CO CI CT

64. – 64 – 15-213, F’02 Multi-Level Page Tables Given: 4KB (2 12 ) page size 32-bit address space 4-byte PTEProblem: Would need a 4 MB page table! 2 20 *4 bytes Common solution multi-level page tables e.g., 2-level table (P6) Level 1 table: 1024 entries, each of which points to a Level 2 page table. Level 2 table: 1024 entries, each of which points to a page Level 1 Table... Level 2 Tables