1. CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

2. CML CMLAnnouncements This Lecture: Review, Virtual Memory Finals –Tuesday, Dec 08, 2009 –Please come on time (You’ll need all the time) –Open book, notes, and internet –No communication with any other human

3. CML CML Course Objectives Understand MIPS assembly language, and write assembly language programs for simple problems, including function calls. Understand the data representation (2’s complement, single and double precision float point) inside the processor, and perform arithmetic operations on them. Understand the working of a single-cycle, and pipelined processor, including basic schemes of hazard detection and avoidance. Understand the rationale behind the memory organization, and know how caches operate. Introduction to multi-cores

4. CML CML Other Aspects of the course Get the key point of the lecture Stimulate thinking Relate course material to outside world Grading as “carrot” and not as “stick”

5. CML CML Feedback for the next generation Attendance Project deadlines Quizzes, Midterms and Finals Assignments Lectures Other issues?

6. CML CML Time, Time, Time Making a Single Cycle Implementation is very easy –Difficulty and excitement is in making it fast Two fundamental methods to make Computers fast –Pipelining –Caches Parallelism –Multi-tasking AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

7. CML CML Virtual Memory How to run two programs simultaneously? Physical memory Size –What if I have less than 2^32 size memory? –Can I use more than 2^32 size memory? Some basic protection mechanisms –One program can overwrite instructions of Operating System functions.

8. CML CML Motivation 1: DRAM a “Cache” for Disk The full address space is quite large: –32-bit addresses: ~4,000,000,000 (4 billion) bytes –64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes Disk storage is ~30X cheaper than DRAM storage –8 GB of DRAM: ~ $12,000 –8 GB of disk: ~ $400 To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk 8 GB: ~$400 256 MB: ~$400 4 MB: ~$400 DiskDRAMSRAM

9. CML CML Motivation #2: Memory Management Multiple processes can reside in physical memory. How do we resolve address conflicts? Reserved Text (Code) Static Data Not yet allocated Stack Dynamic Data 0000 03FF 8000 0000 Reserved Not yet allocated 0000 0001 2000 0000 0000 0000 0001 0000 $gp $sp e.g., what if two different Alpha processes access their stacks at address 0x11fffff80 at the same time? (Virtual) Memory Image for Alpha Process

10. CML CML Process 1: Virtual AddressesPhysical Addresses VP 1 VP 2 Process 2: PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (Read-only library code) Soln: Separate Virtual Addr. Spaces –Virtual and physical address spaces divided into equal-sized blocks “Pages” (both virtual and physical) –Each process has its own virtual address space operating system controls how virtual pages as assigned to physical memory

11. CML CML Motivation #3: Protection Page table entry contains access rights information –hardware enforces this protection (trap into OS if violation occurs) Page Tables Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

12. CML CML VM Address Translation V = {0, 1,..., N–1} virtual address space P = {0, 1,..., M–1} physical address space MAP: V  P U {  } address mapping function N > M MAP(a) = a' if data at virtual address a is present at physical address a' in P =  if data at virtual address a is not present in P Processor Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  missing item fault physical address OS performs this transfer (only if miss)

13. CML CML virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Notice that the page offset bits don't change as a result of translation VM Address Translation Parameters –P = 2 p = page size (bytes). Typically 1KB–16KB –N = 2 n = Virtual address limit –M = 2 m = Physical address limit

14. CML CML Page Tables Page Table (physical page or disk address) Physical Memory Disk Storage Valid 1 1 1 1 1 1 1 0 0 0 Virtual Page Number

15. CML CML Address Translation via Page Table virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1pm–1 n–10p–1p page table base register if valid=0 then page not in memory valid physical page number access VPN acts as table index Address

16. CML CML Page Table Operation Translation –Separate (set of) page table(s) per process –VPN forms index into page table Computing Physical Address –Page Table Entry (PTE) provides information about page if (Valid bit = 1) then page in memory. –Use physical page number (PPN) to construct address if (Valid bit = 0) then page in secondary memory –Page fault –Must load into main memory before continuing Checking Protection –Access rights field indicate allowable access e.g., read-only, read-write, execute-only typically support multiple protection modes (e.g., kernel vs. user) –Protection violation fault if don’t have necessary permission

17. CML CML CPU Trans- lation Cache Main Memory VAPA miss hit data Integrating VM and Cache Most Caches “Physically Addressed” –Accessed by physical addresses –Allows multiple processes to have blocks in cache at same time –Allows multiple processes to share pages –Cache doesn’t need to be concerned with protection issues Access rights checked as part of address translation Perform Address Translation Before Cache Lookup –But this could involve a memory access itself –Of course, page table entries can also become cached

18. CML CML CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss Speeding up Translation with a TLB “Translation Lookaside Buffer” (TLB) –Small, usually fully associative cache –Maps virtual page numbers to physical page numbers –Contains complete page table entries for small number of pages

19. CML CML Address Translation with a TLB virtual address virtual page number page offset physical address N–10p–1p validphysical page numbertag valid dirty valid tagdata = cache hit tagbyte offset index = TLB hit process ID TLB Cache

20. CML CML Yoda says… May the Force be with you