1. 数字系统设计 I 1 2014 ZDMC 存储器与可编程逻辑阵列 April 29, 2014 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程系

2. 数字系统设计 I 2 2014 ZDMC Computer System 计算机系统

3. 数字系统设计 I 3 2014 ZDMC ROM （ Read Only Memory ），只读存储器  ROM 是各种存储器中结构最简单的一种。在正常工作时 它存储的数据是固定不变的，只能读出，不能随时写入.  分类  固定 ROM ：无法更改，出厂时厂家编程  可编程 ROM （ PROM ）：用户可写入一次  可擦可编程 ROM （ EPROM ）：紫外线擦除  电抹可编程 ROM （ EEPROM ） : 电可擦

4. 数字系统设计 I 4 2014 ZDMC 电路结构框图 n 线 ---2 n 线译码器 二进制译码器 地址输入地址输入 容量概念： “ 字 ” 线：只有一个有效 “ 位 ” 线：数据线 地址线： A 0 A 1. A n-1 0 单元 1 单元 2 n -1 单元 W0W0 W1W1.................. D0D0 D1D1 D b-1 数据输出 地址译码器地址译码器 存储矩阵 输出缓冲器 OE 三态 控制 容量 = 字 × 位 （ bits ） 例 EPROM 27256 共有 15 位地址， 8 位输出， 其容量： 注意： 1k=1024 1M=1024K 1G=1024M 核心

5. 数字系统设计 I 5 2014 ZDMC CMOS-ROM 4×2 存储单元矩阵 有源负载 地址码输入端 2-4 线译码器 输出缓冲器 A 1 A 0 =00 时， W 0 =1 ， MOS 导通， 字线处于低电平， D 0 =1 。 接 MOS 表示存储 “1” 没接 MOS ，字线处于高电平， D 1 =0 表示存储 “0” 地址译码器 实现 “ 与 ” 功能： 与阵列 存储矩阵实现 “ 或 ” 功能： “ 或阵 ”

6. 数字系统设计 I 6 2014 ZDMC Typical timing for a ROM read operation

7. 数字系统设计 I 7 2014 ZDMC 另外： ROM 看成查找表（ LUT ， Look-Up Table ）系统 输入地址信号即为电路的输入逻辑变量 地址译码器产生 2 n 个字线即为固定与阵列产生 2 n 个乘积项 存储矩阵即为或阵列把乘积 项组合成 m 个逻辑函数输出。 ROM 应用 (ROM Applications)

8. 数字系统设计 I 8 2014 ZDMC 方法： “ 查找表 ” ，将真值表存于 ROM 中。 例：用一个 ROM 实现二进制码到格雷码的转换 ROM 为组合电路器件： 实现组合逻辑函数，实现时序电路 中组合逻辑部分.

9. 数字系统设计 I 9 2014 ZDMC 确定地址和输出 输入变量为 B 3 、 B 2 、 B 1 、 B 0 ，地址为 4 位；函数 R 3 、 R 2 、 R 1 、 R 0 ， 输出为 4 个，应选用 2 4 ×4 的 ROM 逻辑图 ： ROM 2 4 ×4 01230123 A 0 15 [0]A [1]A [2]A [3]A CS OE 存储内容（数据）： 地址数据 D 3 D 2 D 1 D 0 00000 10001 20011 …… 151000

10. 数字系统设计 I 10 2014 ZDMC 例. 用 ROM 和寄存器实现同时模 10 加 / 减可逆计数器， X=0 ，加法； X=1 ，减法。 模 10 计数状态需 4 位，所以选用 4 位寄存器。根据时序电路结构，可得框图： 图中组合电路由 ROM 实现；而由寄存器作记忆电路。 Reg CP Q 4 4 组合电路 Y （进位） X D

11. 数字系统设计 I 11 2014 ZDMC 确定地址和输出 输入变量为 Q 3 、 Q 2 、 Q 1 、 Q 0 和 X ，地址为 5 位； 输出 D 3 、 D 2 、 D 1 、 D 0 和 Y ， 5 个，应选用 2 5 ×5 的 ROM 逻辑图： 存储内容（数据）： 地址数据 0000000001 00010 …… 0100001001 10000 10~1500000 1000011001 1000100000 …… 1100000111 1100101000 26~3100000 ROM 2 5 ×5 0123401234 A 031 031 [0]A [1]A [2]A [3]A [4]A CS OE CP REG X 加法 计数 减法 计数 状态未用

12. 数字系统设计 I 12 2014 ZDMC 例：用 ROM 设计一个组合电路，该电路输入是 3 位二进制 数，输出是输入数值的平方。  列出组合电路的真值表。一 般情况下真值表中所有可能 的输入和输出都要列出。 列出组合电路的真值表。一 般情况下真值表中所有可能 的输入和输出都要列出。  三个输入端对应 8 个字，每个 字 4 位，因此 ROM 的容量是 8x4 。 8x4ROM A0 A1 A2 B0 B1 B2 0 B3 B4 B5 A2A1A0B5B4B3B2 0000000 0010000 0100001 0110010 1000100 1010110 1101001 1111100 ROM 真值表

13. 数字系统设计 I 13 2014 ZDMC 电路真值表 输入输出 A2A1A0B5B4B3B2B1B0 十进制 0000000000 0010000011 0100001004 0110010019 10001000016 10101100125 11010010036 11111000149 输出 B0 等于输入 A0, 输出 B1 一直为 0. 本例中有三个输入端和四个输出端本例中有三个输入端和四个输出端。

14. 数字系统设计 I 14 2014 ZDMC SARM General Memory Operation (Static Random-Access Memory)

15. 数字系统设计 I 15 2014 ZDMC Typical SRAM Organization: 16-word x 4-bit SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell SRAM Cell -+ Sense Amp -+ -+ -+ :::: Word 0 Word 1 Word 15 Dout 0Dout 1Dout 2Dout 3 -+ Wr Driver -+ -+ -+ Address Decoder WrEn Din 0Din 1Din 2Din 3 A0 A1 A2 A3

16. 数字系统设计 I 16 2014 ZDMC Static RAM Cell ( 静态随机访问存储器单元 ) Random-Access Memory  Read operation:  1. Select row  2. Cell pulls one line low and one high  3. Sense output on bit and bit  Write operation:  1. Drive bit lines (e.g, bit=1, bit=0)  2. Select row  Why does this work?  When one bit-line is low, it will force output high; that will set new state 6-Transistor SRAM Cell bit word (row select) 10 01

17. 数字系统设计 I 17 2014 ZDMC  Write Enable is usually active low (WE_L)  Din and Dout are combined to save pins:  A new control signal, Output Enable (OE_L)  WE_L is asserted (Low), OE_L is unasserted (High) –D serves as the data input pin  WE_L is unasserted (High), OE_L is asserted (Low) –D is the data output pin  Neither WE_L and OE_L are asserted? –Chip is disconneted  Never both asserted! A DOE_L 2 N “words” x M bit SRAM N M WE_L Logic Diagram of a Typical SRAM or chipSelect (CS) + WE

18. 数字系统设计 I 18 2014 ZDMC Typical SRAM Timing Write Timing: D Read Timing: WE_L A Write Hold Time Write Setup Time A DOE_L 2 N words x M bit SRAM N M WE_L Data In Write Address OE_L High Z Read Address Junk Read Access Time Data Out Read Access Time Data Out Read Address OE determines direction Hi = Write, Lo = Read Writes are dangerous! Be careful! Double signaling: OE Hi, WE Lo

19. 数字系统设计 I 19 2014 ZDMC Digital System Family Tree

20. 数字系统设计 I 20 2014 ZDMC inputs AND array outputs OR array product terms Programmable Logic Arrays (PLAs)  Pre-fabricated building block of many AND/OR gates  Actually NOR or NAND  ” Personalized" by making or breaking connections among gates  Programmable array block diagram for sum of products form

21. 数字系统设计 I 21 2014 ZDMC example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate 1 = term connected to output 0 = no connection to output input side: output side: productinputsoutputs termABCF0F1F2F3 AB11–0110 B'C–010001 AC'1–00100 B'C'–001010 A1––1001 reuse of terms Enabling Concept  Shared product terms among outputs

22. 数字系统设计 I 22 2014 ZDMC Before Programming  All possible connections available before "programming"  In reality, all AND and OR gates are NANDs

23. 数字系统设计 I 23 2014 ZDMC Simplified PLD Symbology

24. 数字系统设计 I 24 2014 ZDMC After Programming  Unwanted connections are "blown"  Fuse (normally connected, break unwanted ones)  Anti-fuse (normally disconnected, make wanted connections)

25. 数字系统设计 I 25 2014 ZDMC notation for implementing F0 = A B + A' B' F1 = C D' + C' D AB+A'B' CD'+C'D AB A'B' CD' C'D ABCD Alternate Representation for High Fan-in Structures  Short-hand notation--don't have to draw all the wires  Signifies a connection is present and perpendicular signal is an input to gate

26. 数字系统设计 I 26 2014 ZDMC ABCF1F2F3F4F5F6 000001100 001010111 010010111 011010100 100010111 101010100 110010100 111110011 full decoder as for memory address bits stored in memory Programmable Logic Array Example  Multiple functions of A, B, C  F1 = A B C  F2 = A + B + C  F3 = A' B' C'  F4 = A' + B' + C'  F5 = A xor B xor C  F6 = (A xnor B xnor C) ’

27. 数字系统设计 I 27 2014 ZDMC 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example  BCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C

28. 数字系统设计 I 28 2014 ZDMC not a particularly good candidate for PLA implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete AND and OR gates minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' PLA Design Example (cont ’ d)  Code converter: programmed PLA

29. 数字系统设计 I 29 2014 ZDMC 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = X = Y = Z = ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example  BCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C

30. 数字系统设计 I 30 2014 ZDMC 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D A B C minimized functions: W = X = Y = Z = ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11––––––ABCDWXYZ00000000000100010010001100110010010001100101111001101010011110111000100110011000101–––––11–––––– 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X D A B C K-map for WK-map for X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D A B C K-map for Y PLA Design Example #1  BCD to Gray code converter K-map for Z 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X D A B C BC’

31. 数字系统设计 I 31 2014 ZDMC PLA Design Example #2  Magnitude comparator 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 D A B C 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 D A B C 0 0 1 0 0 0 1 1 0 1 1 1 0 0 D A B C 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 D A B C K-map for EQ K-map for NE K-map for GT K-map for LT

32. 数字系统设计 I 32 2014 ZDMC multiplexerdemultiplexer4x4 switch control Multiplexer / Demultiplexer: Making Connections  Direct point-to-point connections between gates  Multiplexer: route one of many inputs to a single output  Demultiplexer: route single input to one of many outputs

33. 数字系统设计 I 33 2014 ZDMC two alternative forms for a 2:1 Mux truth table functional form logical form AZ0I01I1AZ0I01I1 I1I0AZ00000010010101101000101111011111I1I0AZ00000010010101101000101111011111 Z = A' I 0 + A I 1 Multiplexers/Selectors  Multiplexers/Selectors: general concept  2 n data inputs, n control inputs (called "selects"), 1 output  Used to connect 2 n points to a single point  Control signal pattern forms binary index of input connected to output

34. 数字系统设计 I 34 2014 ZDMC  2:1 mux:Z = A' I0 + A I1  4:1 mux:Z = A' B' I0 + A' B I1 + A B' I2 + A B I3  8:1 mux:Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7  In general, Z =  (m k I k )  in minterm shorthand form for a 2 n :1 Mux 2 -1 I0 I1 I2 I3 I4 I5 I6 I7 A B C 8:1 mux Z I0 I1 I2 I3 A B 4:1 mux Z I0 I1 A 2:1 mux Z k=0 n Multiplexers/Selectors (cont'd)

35. 数字系统设计 I 35 2014 ZDMC control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 control signal A chooses which of the upper or lower mux's output to gate to Z alternative implementation C Z A B 4:1 mux 2:1 mux I4 I5 I2 I3 I0 I1 I6 I7 8:1 mux Cascading Multiplexers  Large multiplexers implemented by cascading smaller ones Z I0 I1 I2 I3 A I4 I5 I6 I7 B C 4:1 mux 2:1 mux 8:1 mux

36. 数字系统设计 I 36 2014 ZDMC C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 F Multiplexers as Lookup Tables (LUTs)  2 n :1 multiplexer implements any function of n variables  With the variables used as control inputs and  Data inputs tied to 0 or 1  In essence, a lookup table  Example:  F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)

37. 数字系统设计 I 37 2014 ZDMC ABCF00010010010101101000101011011111ABCF00010010010101101000101011011111 C' C' 0 1 AB S1S0 F 01230123 4:1 MUX C' C' 0 1 F C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 Multiplexers as LUTs (cont ’ d)  2 n-1 :1 mux can implement any function of n variables  With n-1 variables used as control inputs and  Data inputs tied to the last variable or its complement  Example:  F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)

38. 数字系统设计 I 38 2014 ZDMC  Generalization  Example: F(A,B,C,D) implemented by an 8:1 MUX n-1 mux control variables single mux data variable four possible configurations of truth table rows can be expressed as a function of I n choose A,B,C as control variables multiplexer implementation I 0 I 1...I n-1 I n F....00011....10101 0I n I n '1 C AB 0123456701234567 1 D 0 1 D’ D D’ D’ S2 8:1 MUX S1S0 10101010 10 D A1 11011101 01100110 B C Multiplexers as LUTs (cont ’ d)

39. 数字系统设计 I 39 2014 ZDMC 1:2 Decoder: O0 = G  S’ O1 = G  S 2:4 Decoder: O0 = G  S1’  S0’ O1 = G  S1’  S0 O2 = G  S1  S0’ O3 = G  S1  S0 3:8 Decoder: O0 = G  S2’  S1’  S0’ O1 = G  S2’  S1’  S0 O2 = G  S2’  S1  S0’ O3 = G  S2’  S1  S0 O4 = G  S2  S1’  S0’ O5 = G  S2  S1’  S0 O6 = G  S2  S1  S0’ O7 = G  S2  S1  S0 Demultiplexers / Decoders  Decoders / demultiplexers: general concept  Single data input, n control inputs, 2 n outputs  Control inputs (called “ selects ” (S)) represent binary index of output to which the input is connected  Data input usually called “ enable ” (G)

40. 数字系统设计 I 40 2014 ZDMC demultiplexer generates appropriate Min-term based on control signals (it "decodes" control signals) Demultiplexers as General-Purpose Logic  n:2 n decoder implements any function of n variables  With the variables used as control inputs  Enable inputs tied to 1 and  Appropriate min-terms summed to form the function A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC C AB 0123456701234567 S2 3:8 DEC S1S0 “1”

41. 数字系统设计 I 41 2014 ZDMC F1 F2 F3 Demultiplexers as General-Purpose Logic (cont ’ d)  F1 = A' B C' D + A' B' C D + A B C D  F2 = A B C' D ’ + A B C  F3 = (A' + B' + C' + D') AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 DEC Enable CD

42. 数字系统设计 I 42 2014 ZDMC 0A'B'C'D'E' 1 2 3 4 5 6 7 S2 3:8 DEC S1S0 AB 01230123 S1 2:4 DEC S0 F 0 1 2A'BC'DE' 3 4 5 6 7 S2 3:8 DEC S1S0 E CD 0AB'C'D'E' 1 2 3 4 5 6 7AB'CDE Cascading Decoders  5:32 decoder  1x2:4 decoder  4x3:8 decoders 3:8 DEC 0 1 2 3 4 5 6 7ABCDE E CD S2S1S0S2 3:8 DEC S1S0

43. 数字系统设计 I 43 2014 ZDMC decoder 0n-1 Address 2 -1 n 0 1111 word[i] = 0011 word[j] = 1010 bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) j i internal organization word lines (only one is active – decoder is just right for this) Read-only Memories  Two dimensional array of 1s and 0s  Entry (row) is called a "word"  Width of row = word-size  Index is called an "address"  Address is input  Selected word is output

44. 数字系统设计 I 44 2014 ZDMC F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' truth table ABCF0F1F2F3 0000010 0011110 0100100 0110001 1001011 1011000 1100001 1110100 block diagram ROM 8 words x 4 bits/word addressoutputs ABCF0F1F2F3 ROMs and Combinational Logic  Combinational logic implementation (two-level canonical form) using a ROM

45. 数字系统设计 I 45 2014 ZDMC ROM Structure  Similar to a PLA structure but with a fully decoded AND array  Completely flexible OR array (unlike PAL) n address lines inputs decoder 2 n word lines outputs memory array (2 n words by m bits) m data lines

46. 数字系统设计 I 46 2014 ZDMC ROM vs. PLA  ROM  Design time is short (no need to minimize output functions)  Most input combinations are needed (e.g., code converters)  Little sharing of product terms among output functions  Size doubles for each additional input  Can't exploit don't cares  Cheap (high-volume component)  Can implement any function of n inputs  Medium speed  PLA  Design tools are available for multi-output minimization  There are relatively few unique min-term combinations  Many min-terms are shared among the output functions  Most complex in design, need more sophisticated tools  Can implement any function up to a product term limit  Slow (two programmable planes)

47. 数字系统设计 I Expanding Word Size and Capacity 47 2014 ZDMC

48. 数字系统设计 I A system with incomplete address decoding 48 2014 ZDMC