1. Digital Circuits 1 7-1 Introduction Memory information storage a collection of cells store binary information RAM – Random-Access Memory read operation write operation ROM – Read-Only Memory read operation only a programmable logic device

2. Digital Circuits 2 Programmable Logic Device (PLD) ROM PLA – programmable logic array PAL – programmable array logic FPGA – field-programmable gate array programmable logic blocks programmable interconnects

3. Digital Circuits 3 7-2 Random-Access Memory A memory unit stores binary information in groups of bits (words) 8 bits (a byte), 2 bytes, 4 bytes Block diagram

4. Digital Circuits 4 A 1024*16 Memory

5. Digital Circuits 5 Write and Read Operations Write operation Apply the binary address to the address lines Apply the data bits to the data input lines Activate the write input Read operation Apply the binary address to the address lines Activate the read input

6. Digital Circuits 6 Timing Waveforms The operation of the memory unit is controlled by an external device The access time the time required to select a word and read it The cycle time the time required to complete a write operation Read and write operations must synchronized with an external clock

7. Digital Circuits 7 CPU clock – 50 MHz The access/cycle time < 50 ns A write cycle

8. Digital Circuits 8 A read cycle

9. Digital Circuits 9 Types of Memories Static Information are stored in latches remains valid as long as power is applied short read/write cycle Dynamic Information are stored in the form of charges on capacitors the stored charge tends to discharge with time need to be refreshed (read and write back) reduced power consumption Larger memory capacity

10. Digital Circuits 10 Volatile lose stored information when power is turned off SRAM, DRAM Non-volatile Retains its stored information after the removal of power ROM EPROM, EEPROM Flash memory

11. Digital Circuits 11 7-3 Memory Decoding A memory unit the storage components the decoding circuits to select the memory word A memory cell

12. Digital Circuits 12 Internal Construction A RAM of m words and n bits per word m*n binary storage cells Decoding circuits to select individual words k-to-2 k decoder

13. Digital Circuits 13 A 4*4 RAM

14. Digital Circuits 14 Coincident Decoding A two-dimensional selection scheme reduce the complexity of the decoding circuits

15. Digital Circuits 15 A 10-to-1024 decoder 1024 AND gates with 10 inputs per gates Two 5-to-32 decoders 2 * (32 AND gates with 5 inputs per gates) Reduce the circuit complexity and the cycle time

16. Digital Circuits 16 Address Multiplexing The reduce the number of pins in the IC package consider a 64M*1 DRAM 26-bit address lines Multiplex the address lines in one set of address input pins

17. Digital Circuits 17 An exmples RAS – row address strobe CAS – column address strobe

18. Digital Circuits 18 Random Access Memory RAS, CAS Addressing Even to read 1 bit, an entire 64-bit row is read! Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs

19. Digital Circuits 19 Random Access Memory (1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle Write Cycle Timing

20. Digital Circuits 20 7-4 Error Detection And Correction Improve the reliability of a memory unit A simple error detection scheme a parity bit (Sec. 3-8) a single bit error can be detected, but cannot be corrected An error-correction code generates multiple parity check bits the check bits generate a unique pattern, called a syndrome the specific bit in error can be identified

21. Digital Circuits 21 Hamming Code k parity bits are added to an n-bit data word (2 k –1  n + k) The bit positions are numbered in sequence from 1 to n + k Those positions numbered as a power of 2 are reserved for the parity bits The remaining bits are the data bits

22. Digital Circuits 22 Example: 8-bit data word 11000100 Include 4 parity bits and the 8-bit word  12 bits 2 k –1  n + k, n = 8  k = 4 Bit position: 123456789101112 P 1 P 2 1P 4 100P 8 0 1 0 0 Calculate the parity bits: even parity  assumption P 1 = XOR of bits (3, 5, 7, 9, 11) = 1  1  0  0  0 = 0 P 2 = XOR of bits (3, 6, 7, 10, 11) = 1  0  0  1  0 = 0 P 4 = XOR of bits (5, 6, 7, 12) = 1  0  0  0 = 1 P 8 = XOR of bits (9, 10, 11, 12) = 0  1  0  0 = 1 Store the 12-bit composite word in memory. Bit position: 123456789101112 001110010 1 0 0

23. Digital Circuits 23 When the 12 bits are read from the memory Check bits are calculated C 1 = XOR of bits (1, 3, 5, 7, 9, 11) C 2 = XOR of bits (2, 3, 6, 7, 10, 11) C 4 = XOR of bits (4, 5, 6, 7, 12) C 8 = XOR of bits (8, 9, 10, 11, 12) If no error has occurred Bit position: 1234567891011 12 001110010 1 0 0  C = C 8 C 4 C 2 C 1 = 0000

24. Digital Circuits 24 One-bit error error in bit 1 C 1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1 C 2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0 C 4 = XOR of bits (4, 5, 6, 7, 12) = 0 C 8 = XOR of bits (8, 9, 10, 11, 12) = 0 C 8 C 4 C 2 C 1 = 0001 error in bit 5 C 8 C 4 C 2 C 1 = 0101 Two-bit error errors in bits 1 and 5 C 8 C 4 C 2 C 1 = 0101

25. Digital Circuits 25 The Hamming code can be used for data of nay length k check bits 2 k –1  n + k

26. Digital Circuits 26 Single-Error Correction, Double-Error Dection Hamming code Can detect and correct only a single error Multiple errors cannot be detected. Hamming code + a parity bit Can detect double errors and correct a single error. The additional parity bit is the XOR of all the other bits. E.g.: the previous 12-bit coded word 0 0 1 1 1 0 0 1 0 1 0 0 P 13  0 0 1 1 1 0 0 1 0 1 0 0 1 (even parity).

27. Digital Circuits 27 When the word is read from memory If P = 0, the parity is correct; P = 1, incorrect Four cases 1.If C = 0, P = 0, no error 2.If C  0, P = 1, a single error that can be corrected 3.If C  0, P = 0, a double error that is detected but cannot be corrected 4.If C = 0, P = 1, an error occurred in the P 13 bit