1. Unification of VLSI Placement and Floorplanning
Igor L. Markov

2. Outline Introduction Background and early contributions
Floorplanning
Standard-cell placement
Unification of placement and floorplanning
Large-scale mixed-size placement
Applications to large-scale floorplanning
Summary

3. Traditional VLSI Design Flows
Specification
Partitioning
Logic Design
Floorplanning
Physical Design
Placement
Routing
Fabrication
Compaction
Testing

4. Modern VLSI Design Flows
Specification
Our Work
Floorplacement
Physical Synthesis
Logic Design
Partitioning
Physical Design
Floorplanning
Placement
Design For
Manufacturing
Detail Routing
Routing
Compaction
Fabrication
Testing

5. Hand-off from Front-end to Back-end
Source: EETimes

6. Example of Unstable Hand-off (72K Cells, 74% WS)
Uniform WS
WL=15.32e6
Filler Cells/Capo
WL=8.76e6
Min-cut/IBM
WL=11.43e6
ACG/IBM
WL=10.48e6

7. Review: Partitioning & Floorplanning
Facilitates a hierarchical design methodology (older placers not scalable)
Floorplanning: seeks non-overlapping locations for hard and soft blocks
Objectives: minimize area and wirelength
Traditionally assumes “variable-die” (full-chip) layout
Partitioning & Floorplanning allow early estimation of interconnect for logic optimization
The Floorplanning problem consists of a collection of blocks and the objective is to pack the blocks to minimize a certain objective.
Classical Floorplanning has traditionally had two objectives to minimize, the
Area of the packing, to increase the manufacturing yield and a certain measure of the wirelength of the design .
Classical floorplanning formulation assumes a variable die layout and a flat floorplanning instance. There are no fixed out-lines and the objective is to minimize the area of the floorplan without considering the shape of the layout.
Recent research in floorplanning has focussed on developing new representations for floorplans and faster algorithms to evaluate these representations to a floorplan. These include O-tree, B*-tree, Sequence Pair, Transitive closure Graphs etc.

8. Review: Modern Placement
Growing size & complexity of VLSI chips
Design objectives
Wirelength / congestion / timing / power / yield /...
Design constraints
Fixed die / routability / FP constraints / IPs / cell orientations / pin access / signal integrity / …
Layout sophistication motivates research in placement
Can one algorithm excel in all contexts?

9. Requirements for Placers
Must handle 4-10M cells, 1000s macros
Accept fixed ports/pads/pins + fixed cells
Place macros, esp. with variable aspect ratios
Honor targets and limits for net length
Handle a wide range of placement densities (from <25% to 100% occupied) [ICCAD `03]
ECO (incremental) placement [ICCAD `03]
Fix overlaps after logic restructuring
Place a small number of unplaced blocks
Facilitate synergies between tools
E.g., tools for placement and synthesis

10. Review: Design Types ASICs SoCs
Lots of fixed I/Os, few macros, millions of standard cells
Placement densities : 40-80% (IBM)
Flat and hierarchical designs
SoCs
Many more macro blocks, computational cores, IP blocks
Datapaths + control logic
Micro-Processor Random Logic Macros(P RLM)
Hierarchical partitions are placement instances (5-30K)
High placement densities : 80%-98% (low whitespace)
FPGAs
Regular fabrics, fixed-die
CAD tools are specialized, but use common algorithms

11. Fixed-Die Layout 10 years ago placement was done for variable die
Except for FPGAs
Modern ASICs use pre-defined floorplans
Layout area, routing tracks, power lines, etc may be fixed before placement
Area minimization is irrelevant (area is fixed)
New phenomenon: unroutable placements
New phenomenon: whitespace is known a priori
Row utilization % = density % = 100% - whitespace %
Fixed-die layout is harder than variable-die
Can perform variable die with fixed-die tools, but not vice versa
Tools from Cadence, Synopsys, Mentor, IBM explicitly support fixed-die only

12. Large rectangles can represent
Block-based Design
Std-cell Design
Mixed-size Design
Large rectangles can represent
Intellectual Property (IP): hard or soft
Macros, memories, data-paths, analog modules
Modules of unsynthesized logic

13. Interconnect is Important (dominates delay & power @<0.13μm)

14. Placement versus Floorplanning
Mathematically, placement and floorplanning (FP) are the same problem
Seek module locations
Must avoid overlaps between modules
Must observe region constraints
Seek to minimize wirelength (power)
Seek to satisfy delay constraints
Main differences
Scale (number of objects) and algorithms
This work: a unified tool (floorplacer) can dynamically invoke FP or placement

15. Placement vs. Floorplanning
Characteristics
Floor-planners
Placers
Floor-placers
(this work)
Scalable w runtime No
Yes
Scalable w wirelength
Explicit non-overlapping constraints
Can handle large modules
Support for non-rectangular blocks
Limited
Support for soft-rectangular blocks

16. Outline Introduction Background and early contributions
Floorplanning: datastructures and algorithms
Standard-cell placement
Unification of placement and floorplanning
Large-scale mixed-size placement
Applications to large-scale floorplanning
Summary

17. Slicing vs. Non-slicing Floorplans
Slicing FP:
Simpler
Non-slicing FP:
More general

18. Classical Floorplanning
Seeks non-overlapping locations of hard and soft blocks
Objectives: minimize area and/or wirelength
Core area not pre-defined (variable-die layout)
Floorplan representations:
Location-based versus topological
O-Tree, B*-Tree, Sequence Pair, TCG, CBL etc
We use SP, but our methods are generally applicable
Simulated Annealing (SA) used for optimization
The Floorplanning problem consists of a collection of blocks and the objective is to pack the blocks to minimize a certain objective.
Classical Floorplanning has traditionally had two objectives to minimize, the
Area of the packing, to increase the manufacturing yield and a certain measure of the wirelength of the design .
Classical floorplanning formulation assumes a variable die layout and a flat floorplanning instance. There are no fixed out-lines and the objective is to minimize the area of the floorplan without considering the shape of the layout.
Recent research in floorplanning has focussed on developing new representations for floorplans and faster algorithms to evaluate these representations to a floorplan. These include O-tree, B*-tree, Sequence Pair, Transitive closure Graphs etc.

19. Sequence Pair (SP) Proposed by Murata et al. [TCAD ’97]
Two permutations of N blocks capture the geometric relation between each pair of blocks
(<…a…b…>,<…a…b…>)  a is to the left of b
(<…a…b…>,<…b…a…>)  a is above b
Horizontal (Vertical) constraint graphs
Edge ab iff a is to the left of b (a is above b)
Given block dimensions and an SP, can find locations
O(n2)-time (faster!)
O(n log(n))-time
O(n log(log(n)))-time
We use the well known Sequence pair representation in out floorplanner.
This was proposed by Murata, Fujiyoshi, Nakatake and Kajitani. It consists of 2 permutations of N blocks. The order of the blocks in the 2 sequences capture the geometric relation between each pair of blocks.
Specifically for any 2 blocks say a and b, if they are in the same relative order in both the sequences then there is a horizontal constraint between the 2 blocks. Similarly if the relative order of the 2 blocks is reversed then there is a vertical constraint between the 2.
From these relations we can build horizontal and vertical constraint graphs. For eg. In the vertical constraint graph there is a directed edge from a to b iff a is above b as specified by the sequence pair.
After building this graph and adding the sources and sinks we can topologically traverse the graph to compute the block locations as represented by the sequence pair. This algorithm has an O(n2) complexity and is slow because the constraint graphs need to be computed explicitly.
Top
<ABC, BAC> A
Right
Left B C
Bottom

20. Fixed Outline Floorplanning
Not an area minimization problem
Rather a constraint satisfaction problem
“Classical Floorplanning Considered Harmful” [Kahng, ISPD `00]
First addressed in our work [ICCD`01, TVLSI`03]  
Fixed-outline constraints consist of predetermined x-span and y-span of the required layout. The problem is to fit all the blocks of the design into this area without any overlaps while minimizing the wirelength.
In out experiments we fixed the maximum whitespace of our designs to be 15% and calculated the fixed outlines for different aspect ratios of the required layout
Thus the problem is now changed from being a pure minimization problem to that of being a constraints satisfaction problem.
y-span
x-span

21. Floorplan “Slack” (compatible with many FP representations)D F D E E C C B
<FEDBCA,
ABFECD> B A A
<FED> is the LCS
I will now introduce the notion of Floorplan slack. Slack for a particular block corresponds tp the whitespace around that block. For eg for block A the x-slack is given by the x –whitespace around it.
If we have an algorithm which can pack left to right and right to left, we can easily calculate the individual slack of each block as follows.
Note that blocks F E and D lie on the critical path as their x-slacks are 0. Thus any movements to these blocks with this ordering would result in an increase in the span of the floorplan
We also note that blocks cannot have –ve slack as that would result in an overlap between blocks. This is similar to static timing analysis in which –ve slacks mean that we have violated the timing constraints.
Left Packing
Right Packing
x-slack for block A =
x(Aright) – x(Aleft)
x-Slack Computation

22. Example: A Slack-based Move
Block with y-slack=0

23. Fixed-outline FP’er Parquet (based on Simulated Annealing) [Adya&Markov, ICCD 01, TVLSI 03]
Restart 
current outline
S.A.
y-violation
S.A.
S.A. 
x-violation
required outline

24. Global Placement Techniques
Simulated Annealing
TimberWolf
Dragon (Min-cut + SA)
Min-cut partitioning (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui)
Multi-level Fiduccia-Mattheyses
Analytical Placement
Force-directed [Cheng & Kuh 84]
PROUD [Tsay & Kuh 88]
GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91]
Geometric Partitioning [Vygen 97]
Poisson equation [Eisenmann & Johannes, DAC ‘98]
ACG [Alpert et al, ICCAD 2002]

25. Outline Introduction Background and early contributions
Floorplanning
Standard-cell placement
Unification of placement and floorplanning
Applications to large-scale mixed-size placement
Applications to large-scale floorplanning
Summary

26. Global Placement by Recursive Min-cut Partitioning
Placement Bin 1 2
End-case placement by branch-and-bound
etc. 3 4
Placers using min-cut bisection: Capo, FengShui, IBM CPlace, Cadence QPlace

27. Detail: Partitioning One Bin
Tentative Cut-line
100%
area
50%
50%

28. Detail: Partitioning One Bin
Shift cutline to
equalize density
60%
40%
50%
50%

29. Detail: Partitioning One Bin
Actual cutline
60%
40%
60%
40%

30. Min-cut Placement Can Produce Slicing Floorplans
We are going to use this effect for floorplanning
Potential reductions in run-time and wirelength
Recall: traditional approaches use Simulated Annealing
Slicing
Floorplan!

31. Outline Introduction Background and early contributions
Floorplanning
Standard-cell placement
Unification of placement and floorplanning
Large-scale mixed-size placement
Applications to large-scale floorplanning
Summary

32. Why Mixed-size Placement is Difficult
IP reuse, memories etc  large rectangles in layout
Mixed-size placement is at least as hard as
Standard cell placement (many small movable modules)
Floorplanning (large, bulky modules are difficult to pack, especially on a fixed die!)
Typical optimization heuristics are move-based
Each move is “local”, i.e., affects few other objects
However, large modules affect many other modules
Some moves have ripple-effect on small cells
Removing overlaps after global placement is not easy, invalidates top-down estimation

33. Cadence-recommended Mixed-size Placement Flow
QPlace (SEDSM) places large modules first
Designer manually removes overlaps
From now on, modules are considered fixed
QPlace is called to place standard-cells
Otherwise, as our experiments show,
Handling many large cells is not ideal in QPlace

34. Cadence (SEDSM/QPlace) Screenshot (v. 5.1.67 in 2002)

35. Cadence (SEDSM / QPlace) Screenshot (v. 5.4.126 in 2004)

36. Relevant Academic Work : Continuous Optimization
Force directed approaches
[Eisenmann, Johannes, DAC ‘98] : mixed-size
Wires modelled as attractive forces
Overlaps modelled as repelling forces
Are good with a lot of white-space in design
Otherwise, designer must remove overlaps

37. Relevant Academic Work : Combinatorial Optimzation
Particularly promising on constrained designs
[Adya & Markov, ISPD `02]: Min-cut Placement + Floorplanning
[Cong et. al, ASPDAC `03]: Multi-level SA placement
[Adya&Markov, ICCAD `03]: Better whitespace distribution
[Madden et. al, ISPD `04]: Min-cut placement Post Placement Legalization
This work : Floorplacement

38. Capo+Parquet Flow [Adya & Markov, ISPD ’02]
Proposed pre-processing techniques for solving the mixed-size placement problem
Can be used with standard-cell placers
Main approach: loose integration of floorplanning and placement
Apparently the first publication to reliably achieve overlap-free placements
Contributed mixed-size benchmarks
Now widely used in the placement literature

39. Capo+Parquet Flow [Adya & Markov, ISPD ’02] (Outline)
Generate initial placement using a standard-cell placer
Generate a fixed-outline floorplanning instance by “physical clustering”
Remove overlaps and generate valid macro locations using a fixed-outline floorplanner
Place small cells again using standard-cell placer with macros considered fixed

40. Mixed-size Flow (Capo+Parquet) [Adya&Markov, ISPD ’02]
Initial Placement
Floorplanned design
Final Placement

41. Shredding Macro Cells Va Vr Shred all macros into smaller sub-cells
Place shredded netlist using a black-box min-WL placer
Determine location of macros by averaging locations of sub-cells
(Should work with many min-WL placers)
Fake
std-cell Va 3 Vr 2
MACRO 1
Fake
wires 1 2

42. Shredding + Analytical Incremental Legalization [Adya&Markov, TODAES ’04]
Initial Placement
Final Placement

43. Integrated Partitioning, Floorplanning and Placement
Traditional design flows apply separate optimizations
Mostly a scalability concern for old algorithms
New generation of fast min-cut placers enable an integrated approach
A min-cut partitioner is part of the placer
Shifting cut-lines perform floorplanning
End result: locations of modules (a placement)

44. Our New Approach: Direct Integration of Placement & Floorplanning
We use top-down placement, fall back on floorplanning when necessary (many “local” calls to a floorplanner)
In a mixed-size placement problem, can start with several slicing cuts
Eventually will need to pack blocks (when exactly?)
This allows to solve fixed-outline floorplanning
In rare cases, packing may be infeasible (what can be done then?)

45. Placement by Recursive Bisection + Fixed-outline floorplanning
etc.
Placement bin needs
Floorplanning

46. Our Floorplacement Algorithm
Variables: queue of placement bins
Initialize: queue with top-level bin
While (queue not empty)
Dequeue a bin
If (bin has large/many macros)
Cluster std-cells into soft blocks
Use fixed–outline floorplanner to pack all macros
Fix macros
else if (small enough)
Process end case
else
Bi-partition the bin into smaller bins
Enqueue each child bin

47. Floorplacement Example
Placement bin needs floorplanning
Cut-line
(min-cut)

48. When to Floorplan ? Large-macro tests
At least 1 macro does not fit in child bins
<30 macros total, with total area > 80% of bin area
What if fixed-outline floorplanning fails ?
Return to previous level of placement hierarchy
Merge two child bins to form a parent bin
Try area-only floorplanning
Else final placement has overlaps (can try legalizing it at the end!)
Above conditions detect block-based designs, std-cell and mixed-size designs

49. Mixed-size Placements
Design A: ibm01
Design B: Faraday RISC

50. Empirical Results : Placement vs. Floorplacement
Capo8.5+Parquet
(2002)
Capo8.8+KraftWerk
(2003)
mPG
(2003)
Cadence
SEDSM (2004)
Capo9.0
(Floorplacement)
ckt WL
Time
ibm01
3.05 2m
2.92 5m
3.01 9m
3.36
10m
2.77
4.9m
ibm02
6.83
6.5
11m
7.42
18m
6.79
19m
5.60
ibm10
45.46
35m
47.5
68m
43.6
86m
41.02
89m
36.31
59m
ibm15
65.0
93m
66.8
122m
65.5
192m
64.99
268m
59.91
121m
ibm18
51.84
110m
57.2
158m
50.7
220m
53,81
316m
50.9
78m
Avg%
-14.88
-10.07
-9.46
-7.72

51. Empirical Results: Floorplanning vs. Floorplacement
GSRC Circuit
#Blks
Parquet (Floorplanner)
Capo9.0 (Floorplacer) WL
Time (sec)
#Min-cut levels
N10 10
5.58
0.27
5.57
0.37
N30 30
17.38
2.35
16.93
1.89 1
N50 50
20.77
8.16
20.34
5.3
N100
100
34.53
50.12
32.39
10.5 2
N200
200
62.28
240.6
56.82
27.4 3
N300
300
75.69
433.9
63.62
25.2

52. Floorplanning vs. Free-shape Floorplacement
Rectangular shapes during floorplanning seem arbitrary
Instead, can shred blocks into fake standard cells (+fake wires)
Apply traditional placement
Shape blocks, minimize WL
Rect- angular
Free-shape
Circuit
Parquet
Shred+ Capo9.0
Avg %
Ami33
76987
46072
40.1
Ami49
895560
469476
47.5
N50
202240
87957
56.5
N100
350593
157548
55.0

53. What About Timing-Driven Placement and Floorplanning ?
Net-weights, net-bounds etc. extend wirelength-driven design flows to timing-driven design flows
Our techniques improve cycle times for commercial chips within the physical synthesis flow w Amplify ASIC [Adya et. al, ICCAD `03]
Similar techniques used at IBM
Upcoming DAC `04 papers
“Efficient Timing Closure w/o Timing-driven Placement and Routing”, U. Washington [16.3]
Performance Optimization in Microarchitectural Floorplanning, GATech [38.1]
Extends our software (Parquet) for timing optimization

54. Summary
A hybrid algorithm which combines min-cut partitioner and fixed-outline floorplanner
A software tool for large-scale chip design
Partitioning
Wirelength-driven floorplanning
Standard-cell and mixed-size placement
Directly applicable to low-power design, can be adapted to performance optimization
DAC`03/`04 papers from UCLA/GATech use Parquet
Facilitate user-friendly design methodologies
Hide artifacts of algorithm development from chip designers

55. Relevant Publications: Conferences
S.N. Adya, S.C. Chaturvedi, D.A. Papa and I.L. Markov, “Unification of VLSI Placement and Floorplanning",submitted to ICCAD, 2004.
D.A. Papa, S.N. Adya and I.L. Markov, "Constructive Benchmarking for Placement", Great Lakes Symposium on VLSI (GLSVLSI), 2004.
S.N. Adya, I.L. Markov and P.G. Villarrubia, ”On Whitespace and Stability in Mixed-size Placement and Physical Synthesis”, International Conference on Computer Aided Design (ICCAD), pp , 2003.
S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, "Benchmarking for Large-scale Placement and Beyond", International Symposium on Physical Design (ISPD), pp , 2003
S.N. Adya, I.L. Markov and P.G. Villarrubia, "Improving Min-cut Placement for VLSI Using Analytical Techniques", IBM ACAS Conference, pp , 2003.
S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement", International Symposium of Physical Design (ISPD), pp.12-17, 2002. 
S.N. Adya and I.L. Markov, "Fixed Outline Floorplanning Through Better Local Search", International Conference of Computer Design (ICCD), pp , 2001

56. Relevant Publications: Journals
S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, “Benchmarking for Large-scale Placement and Beyond”, IEEE Trans. on CAD, vol 23(4), April, 2004, pp
S.N. Adya and I.L. Markov, “Combinatorial Techniques for Mixed-size Placement”, to appear in ACM Trans. on Design Automation of Electronic Systems, 2004
S.N. Adya and I.L. Markov, “Fixed-outline Floorplanning : Enabling Hierarchical Design”, IEEE Trans. on VLSI, vol. 11(6), December 2003, pp  
S.N. Adya, I. L. Markov and P. G. Villarrubia, “On Whitespace and Stability in Physical Synthesis”, in Preparation, 2004.

57. Thank You !

58. Overview: Whitespace Management Framework
Need to handle a wide range of placement densities (<25% to 100%)
Alpert, Nam & Villarrubia [ICCAD `02]
Physical synthesis constraints
Minimum local whitespace required for buffer insertion, driver upsizing and routability
Uniform WS distribution helps achieving this
For large whitespace
Uniform WS distribution  higher wirelength
Related work at ICCAD `02
Analytical Constraint Generation (ACG)

59. Circuit Example: 72K Cells, 74% WS
Uniform WS
WL=15.32e6
Filler Cells/Capo
WL=8.76e6
Min-cut/IBM
WL=11.43e6
ACG/IBM
WL=10.48e6

60. Filler cells in context of Physical Synthesis

61. Overview: Stability of Placement Algorithms
Local whitespace may not be enough to keep the same global placement
E.g., increased local whitespace requirement to fix congestion or keep more space for buffers
One may need to re-place everything
We would like to preserve relative placements, but min-cut placers & annealers are very unstable
Stability of placement algos is important to physical synthesis loops
Enables iterative improvement of various objectives (timing / congestion etc.)

62. Example: Lack of Stability
Demonstrated Using Congestion Maps
IBM02-v2 Design
Placer: Capo (Randomized)

63. Stability of Placement Algorithms
Inherently stable algorithms
Analytical: quadratic, force-directed,…
Algorithms that lack stability
Min-cut and Simulated Annealing
Very different solutions produced if netlist or floorplan change a little
Our solution: relative stability
From run to run
Tie one placement to another

64. Proposed Flow Generate initial placement
Tether x% of the cells to the locations specified by initial placement
Add fixed pins and fake nets
Rerun placement
Remove fake pins and nets
Tethering offers a tunable amount of freedom for further optimization
See detailed data in the paper

65. Tethering a Cell to a Location
Generate initial placement
Tether random x % of cells to initial locations
Use fake zero-width pins and fake nets
Tunable parameters
Size of tethering box
Number of cells tethered
Fake Pin
Fake Net

66. Improving Stability of Min-cut Placers
Capo (randomized min-cut)
Initial
0% tether
5% tether

67. Overview: Rescaling Shorter design cycles  IP reuse
# of repeaters are increasing rapidly as we migrate to newer process nodes
Wires are not scaling as well as devices
More # of repeaters / logic gate
Different minimum local whitespace requirements for a block during migration
Want to preserve relative timing characteristics of a design
Rescaling

68. Overview: Reshaping Floorplan often changes during the design process
Blocks are carefully optimized for layout
When changing the block shape
A designer may want to maintain the relative timing characteristics of the design

69. Reshaping / Rescaling

70. Rescaling flow Xnew = Xold * Widthnew / Widthold
Rescale Formula:
Xnew = Xold * Widthnew / Widthold
Ynew = Yold * Heightnew / Heightold

71. Reshaping Flow

72. Pin Rotation

73. Designs used for our Experiments
Downloaded from

74. Placer: Cadence Qplace
Rescale Results
Placer: Cadence Qplace

75. Placer: Cadence Qplace
Reshape Results
Placer: Cadence Qplace

76. Summary: Stability
Seemingly unstable algorithms can be made relatively stable
Pick a small subset of cells (at random?)
Tether each to an initial location (using fake terminals and nets)
Trade-off
Freedom for further optimization versus placement similarity

77. Algos: Placement vs. Floorplanning
Part of Amplify-ASIC
Academic
Placement
Industrial
Placement
Capo8.7
Academic
Floorplanning
Industrial
Floorplanning
Parquet

78. Routing Results on Faraday Mixed-size Benchmarks
Ckt
SEDSM (2004)
Capo9.0
Place
Route WL
cpu
(sec)
DMA
4.85 70
6.43
167
4.50 98
5.92
186
DSP1
10.09
232
12.28
341
10.68
760
12.6
312
RISC1
17.5
427
22.28
695
17.8
1243
23.36
1431
DSP2
9.88
191
12.04
235
9.85
11.66
RISC2
16.58
306
22.36
697
17.85
1091
23.37
650

79. Fixed-Outline FP Results
Without slack-based moves
Not able to satisfy fixed-outline constraints (!)
With slack-based moves
Fixed-outline success rates for benchmark w 100 blocks

80. Hierarchical Floorplanning (enabled by fixed-outline FP)
Top level : 416 blocks
Bottom level : blocks
WS=17% m
Flat
WS = 55% m

81. Placements: Capo vs. FengShui
(simple legalization may fail)
Capo 9.0

82. Routing Results on IBM-v2 Std-cell benchmarks

83. Analytical Methods Based on a common objective quadratic wirelength
Minimize  w(n)*[ (xi – xj)2 + (yi – yj)2 ]
n  Nets i,j  n
Placers temporarily allow for overlapping cells
Legalization approaches
Min-cut partitioning: PROUD, GORDIAN, GORDIAN-L
Geometric partitioning [Vygen, DAC `97]
Force-directed methods [Eisenmann & Johannes `98]

84. Min Quadratic Soln Partitioned Design