1. Ch5. 기본 컴퓨터의 구조와 설계

2. Ch5. Basic Computer Design

3. Ch5. Basic Computer Design
주소: 직접(direct)주소 vs 간접(indirect)주소
Ch5. Basic Computer Design

4. Ch5. Basic Computer Design
(Example) J-K 플립플롭
J-K 플립플롭
Ch5. Basic Computer Design

5. Ch5. Basic Computer Design
(Example) 4-bit Register with Parallel Load
Ch5. Basic Computer Design

6. Ch5. Basic Computer Design
Computer Registers
Registers for the Basic Computer
Ch5. Basic Computer Design

7. Ch5. Basic Computer Design
(Example) Bus system with multiplexer
Ch5. Basic Computer Design

8. Ch5. Basic Computer Design
(Example) Bus System with Tri-state Buffer
Ch5. Basic Computer Design

9. Ch5. Basic Computer Design
Common Bus System for the Basic Computer
Ch5. Basic Computer Design

10. Ch5. Basic Computer Design
(Example) 메모리 (4096 x 16)
Ch5. Basic Computer Design

11. Ch5. Basic Computer Design
(Example) LD signal
Ch5. Basic Computer Design

12. Ch5. Basic Computer Design
(Example) MUX and Decoder
Ch5. Basic Computer Design

13. Ch5. Basic Computer Design
컴퓨터 명령어
세가지 기본 형식
메모리참조명령어(memory-reference instruction)
레지스터참조명령어(register-reference instruction)
입출력명령어(I/O instruction)
Ch5. Basic Computer Design

14. Ch5. Basic Computer Design
Instruction Set Completeness
1. Arithmetic, logical, and shift instructions
arithmetic operation : addition => ADD, subtraction => CMA, INC, ADD
logic operation : AND, CMA, CLA
shift : CIR, CIL, CLE, CME
2. Instructions for moving information to and from memory and processor registers
LDA, STA
3. Program control instructions together with instructions that check status conditions
BUN, BSA, ISZ, skip
4. Input and output instructions
INP, OUT
Ch5. Basic Computer Design

15. Ch5. Basic Computer Design
Timing and Control
Master clocks
be applied to all F/Fs and registers
do not change the state of a register unless the register is enabled by a control signal
Control Unit
generates the control signals
two major types of control organization
hardwired control
microprogrammed control
Hardwired control
the control logic is implemented with gates, F/Fs, decoders and other digital circuits
can be optimized to produce a fast mode of operation
difficult to change
Microprogrammed control
the control information is stored in a control memory
the control memory is programmed to initiate the required sequence of microoperations
easy to change : by updating the microprogram in control memory
Ch5. Basic Computer Design

16. Ch5. Basic Computer Design
Control Unit of Basic Computer
Ch5. Basic Computer Design

17. Ch5. Basic Computer Design
(Example) D3T4 : SC <= 0
(Example) T0 : AR <= PC
Ch5. Basic Computer Design

18. Ch5. Basic Computer Design
Instruction Cycle
Instruction Cycle
1) Instruction Fetch 2) Instruction Decode 3) Effective Address 4) Instruction Execution
(Cf) Assumption
A memory read or write cycle will be initiated with the rising edge of a timing signal
A memory read or write cycle will be completed by the time the next clock goes through its positive transition
Fetch and Decode Cycle
T0 : AR <= PC
T1 : IR <= M[AR], PC <= PC + 1
T2 : D0, D1, ..., D7 <= Decode IR(12-14), AR <= IR(0-11), I <= IR(15)
Control signal for AR <= PC
S2S1S0 = 010, LD(AR)
Control signal for IR <= M[AR], PC <= PC + 1
Enable the read input of memory, S2S1S0 = 111, LD(IR), INCR(PC)
Ch5. Basic Computer Design

19. Ch5. Basic Computer Design

20. Ch5. Basic Computer Design
Determine the Type of Instruction
D7’IT3 : AR <= M[AR], D7’I’T3 : Nothing, D7I’T3 : Execute a register reference instruction
D7IT3 : Execute an input-output instruction
Ch5. Basic Computer Design

21. Ch5. Basic Computer Design
Register-Reference Instruction
D7I’T3
Ch5. Basic Computer Design

22. Memory Reference Instructions
Effective address in AR
placed there during timing signal T2 when I = 0(indirect mode)
placed there during timing signal T3 when I = 1(direct mode)
AND to AC
D0T4 : DR <= M[AR]
D0T5 : AC <= AC ^ DR, SC <= 0
ADD to AC
D1T4 : DR <= M[AR]
D1T5 : AC <= AC + DR,
E <= Cout, SC <= 0
Load AC
D2T4 : DR <= M[AR]
D2T5 : AC <= DR, SC <= 0
=> Why no direct loading?
Store AC
D3T4 : M[AR] <= AC, SC <= 0
Ch5. Basic Computer Design

23. Ch5. Basic Computer Design
BUN : Branch Unconditionally
D4T4 : PC <= AR, SC <= 0
BSA : Branch and Save Return Address
M[AC] <= PC, PC <= AR + 1
D5T4 : M[AR] <= PC, AR <= AR + 1
D5T5 : PC <= AR, SC <= 0
ISZ : Increment and Skip if Zero
D6T4 : DR <= M[AR]
D6T5 : DR <= DR + 1
D6T6 : M[AR] <= DR, if (DR = 0) then (PC <= PC + 1), SC <=0
Ch5. Basic Computer Design

24. Ch5. Basic Computer Design
Control Flow
Ch5. Basic Computer Design

25. Input-Output and Interrupt
I/O configuration
FGI : input control flag
set when new information is available, clear when the information is accepted by the computer
needed to synchronize the timing rate difference between the input device and the computer
FGO : output control flag
clear when new information is available, set when the information is accepted by output device
Ch5. Basic Computer Design

26. Ch5. Basic Computer Design
I/O instruction
Ch5. Basic Computer Design

27. Ch5. Basic Computer Design
I/O data transfer
1. Program controlled data transfer
inefficient
(Example) instruction cycle time : 1us, maximum transfer rate : 10 character per sec,
Two instructions are executed when the computer checks the flag bit and decides not to transfer the information
=> The computer will check the flag 50,000 times between each transfer
2. Data transfer by interrupt
Interrupt
IEN : interrupt enable F/F
0 : interrupt disable
1 : interrupt enable
R : interrupt F/F
0 : instruction cycle
1 : interrupt cycle
IEN =1 and FGI = 1, IEN = 1 and FGO = 1
R F/F is set to 1
At the end of the execute phase, control checks the value of R, and if it is equal to 1, it goes to an interrupt cycle instead of instruction cycle
F/F R setting condition :
T0’T1’T2’(IEN)(FGI + FGO) : R <= 1
Ch5. Basic Computer Design

28. Ch5. Basic Computer Design

29. Ch5. Basic Computer Design
Interrupt Cycle
Return Address Saving
1. Stack
2. Processor Register
3. Specific Memory Location : Mechanism for Our Basic Computer
Modified Fetch Cycle
T0 => R’T0, T1 => R’T1, T2 => R’T2
Interrupt Cycle
RT0 : AR <= 0, TR <= PC
RT1 : M[AR] <= TR, PC <= 0
RT2 : PC <= PC + 1, IEN <= 0, R <=0, SC <= 0
=> location 0 : location for return address, location 1 : location for interrupt vector
Ch5. Basic Computer Design

30. Complete Computer Description
Ch5. Basic Computer Design

31. Ch5. Basic Computer Design

32. Design of Basic Computer
H/W component of Basic Computer
1. A memory unit with 4096 words of 16bits each
2. Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
3. Seven F/Fs : I, S, E, R, IEN, FGI and FGO
4. Two decoders : a 3 x 8 operation decoder and a 4 x 16 timing decoder
5. A 16-bit common bus
6. Control logic gates
7 Adder and logic circuit connected to the input of AC
Control Logic Gates
input : Figure 5-6
Output
1. Signals to control the inputs of the nine registers
2. Signals to control the read and write inputs of memory
3. Signals to set, clear, or complement the F/Fs
4. Signals for S2, S1, S0 to select a register for the bus
5. Signals to control the AC adder and logic circuit
Ch5. Basic Computer Design

33. Ch5. Basic Computer Design
Control of AR
R’T0 : AR <= PC : Load
R’T2 : AR <= IR(0-11) : Load
D7’IT3 : AR <= M[AR] : Load
RT0 : AR <= 0 : Clear
D5T4 : AR <= AR + 1 : Increment
Control of Memory Read
R’T1 + D7’IT3 + (D0 + D1 + D2 + D6)T4
Ch5. Basic Computer Design

34. Ch5. Basic Computer Design
Control of Single F/F
pB7 : IEN <= ;p = D7IT3
pB6 : IEN <= 0
RT2 : IEN <= 0
Control of Common Bus
S2S1S0 = 001
D4T4 + D5T5
S2S1S0 = 111
R’T1 + D7’IT3 + (D0 + D1 + D2 + D6)T4
Ch5. Basic Computer Design

35. Design of Accumulator Logic
All the statements that change the content of AC
D0T5: AC <= AC ^ DR
D1T5: AC <= AC + DR
D2T5: AC <= DR
pB11: AC(0-7) <= INPR
rB9: AC <= complement AC
rB7: AC <= shr AC, AC(15) <= E
rB6: AC <= shl AC, AC(0) <= E
rB11: AC <= 0
rB5: AC <= AC + 1
Circuits associated with AC
Ch5. Basic Computer Design

36. Ch5. Basic Computer Design
Control of AC Registers
Ch5. Basic Computer Design

37. Ch5. Basic Computer Design
Adder and Logic Circuit
Ch5. Basic Computer Design