1. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Alessandro Bogliolo University of Urbino Nicola Terrassan and Davide Bertozzi University of Ferrara

2. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Outline 1.Motivation 2.Physical channel design 3.Analytical model Design Validation against HSPICE 4.Macromodel integration in SystemC Accuracy assessment 5.Applications and conclusions

3. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Motivation SPICE-based design space explorations are not viable due to system complexity Physical gap Hell of nano-scale physics 500M Transistor Platform Design-Productivity Gap Degradation of RC propagation delay across on-chip interconnects Low-swing signaling and coding for low-power Increased sensitivity to on-chip noise sources Development of accurate physical models and their abstraction into accurate compact models are mandatory for designing complex circuits

4. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Objective of the work Data out FF inFF out Data in Driver RC line Receiver  Communication channel driver, interconnect, receiver, sampling stages Target: 1 GHz operating frequency, low-power, high throughput links  Scalability analysis  From 130 to 90 nm, Berkeley Predictive Technology Models  Analytical model  capturing the effects of on-chip noise sources on the channel sub-systems  based on the noise sensitive area concept Paramet. bit-level model of noisy on-chip communication channels Macromodel integration in SystemC for system-level simulation

5. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Outline 1.Motivation 2.Physical channel design 3.Analytical model Design Validation against HSPICE 4.Macromodel integration in SystemC Accuracy assessment 5.Applications and conclusions

6. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Pseudo-differential interconnect Driver RC Line PDIFF receiver Clocked sense amplifier Static FF Makes use of a single wire per bit while still retaining most advantages of differential signaling: low swing, low sensitivity to supply noise Sources of reliability degradation: mismatches of input pair TNs or REFs

7. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Delay breakdown 130nm technology node Transistor sizing with Hspice optimization engine Vdd=1.2V, Swing=0.2V Interconnect length=2mm (intermediate metal layer)  Maximum Frequency: 1.35Ghz  SAFF Flip Flop and PDIFF receiver are the delay bottlenecks

8. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Delay scalability 130 nm technology node Vdd = 1,2 V Swing = 0,2 V Interconnect length = 2 mm Intermediate metal layer F MAX (130 nm)= 1,35 GHz 90 nm technology node Vdd = 1 V Swing = 0,2 V (to preserve noise margins) Interconnect length = 2 mm Intermediate metal layer F MAX (90 nm)= 1,45 GHz Propagation delay. Logic 1-to-0 transition  Scaling of gate delay  Interconnect delay does not scale (51% degradation)

9. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Power breakdown 130nm 90nm Total Power: 98,968 µW 38,532 µW  Scaling factor of power ranges from 0.24x (SAFF) to 0.52x (NOR Latch)  Interconnect power increases by 1.1x  FF, driver and receiver are the most power-hungry components  Interconnect power relevant only in 90nm  Overall channel power reduces by 60% 30% 7% 26% 7% SAFF Driver RC line PDIFF Latch NOR 19% 27% 20% 24% 10%

10. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Outline 1.Motivation 2.Physical channel design 3.Analytical model Design Validation against HSPICE 4.Macromodel integration in SystemC Accuracy assessment 5.Applications and conclusions

11. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Modelling approach splitting the communication channel in two parts: a driving section and a driven section Data in Driver RC line Receiver FF inFF out Data out Splitting point Driving section Driven section Provides a signal waveform Poses conditions to its shape to guarantee correct sampling Error probability evaluated by comparing the signal provided by the driving section with the requirements posed by the driven section

12. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Noise sensitive areas Receiver requirements modelled through noise sensitive areas: Vin Hold Time t0 Vswing=0.2 Receiv.FF Vin clock Triggering condition: a requirement on the input voltage at sampling time SA-based receiver imposes holding requirements on the input signal: the stronger the signal the shorter the hold time regions in the signal-time plane which are forbidden to the signal waveform

13. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Experimental NSA 130 nm technology node – 10% positive injected noise on Vdd  A positive Vdd variation at the receiver shrinks the NSA The receiver takes less time to sample input signals  Triggering condition reduces to: Vin higher than 0.140V (for sampling a logic 1) Vin lower than 0.065V (for sampling a logic 0) nominal Vin [V] Thold [ps]

14. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Parametric NSA model Measured parameters are manipulated in order to use linear regressions to fit experimental data with a minimum number of fitting coefficients

15. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Model accuracy Analytical models of Thold evaluated for different random combinations of noise sources and Vin values HSPICE sweep simulations conducted with injected noise sources to determine the minimum hold time Results: –Average error: 3.5% in 130 nm (4.95% in 90nm) –Maximum error: 17.53% in 130 nm (23.5% in 90nm) for concurrent common-mode noise on Vref and Vgnd

16. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Driving subcircuit model Data in Driver RC line FF in Vin Time (ps) Far-End Voltage (mV) Far-end signal waveform approximated by a delay followed by an exponential transient

17. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Exponential transient model Logic 0 to 1 transition Logic 1 to 0 transition c is the slope parameter, experimentally approximated by: Almost insensitive to Vref variations Depends on interconnect length (l) Further refined to account for wire parameters: Rw,Cw: resistance and capacitance per unit length Rt: driver output resistance Cr: receiver input capacitance

18. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Delay model Inversely proportional to Vdd - Gnd Directly proportional to Resistance and Capacitance per unit length We did not derive fitting models of the delay measured from HSPICE simulations, but of those delay values that minimize the MSE of the fitting exponential transients We therefore aim at achieving maximum accuracy in predicting the far-end voltage Vin at sampling time

19. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Accuracy Validation against HSPICE for different noise scenarios MSE for exp. transient In practice, the error on Vin is much smaller than MSE at sampling time Time (ps) Far-End Voltage (mV)

20. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Outline 1.Motivation 2.Physical channel design 3.Analytical model Design Validation against HSPICE 4.Macromodel integration in SystemC Accuracy assessment 5.Applications and conclusions

21. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Macromodel integration in SystemC Need: expose the analytical models to a high-level modelling and simulation environment  Interconnect analysis with SPICE accuracy in complex systems  Traditional macromodels integrated in VHDL/Verilog  SystemC is emerging as the ref. backbone for system-level design  C-language programming facilitates HW-SW codesign Analytical macromodel integration in SystemC We exploited the Advanced and Flexible Communication Abstractions in SystemC  Ports: gateways to communication functions  Interfaces: declaration of communication functions  Channels: actual implementation of communication functions

22. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels SystemC communication abstractions sc_signal with Integrated Analytical model HW Module Predefined sc_signal channel (read/write implementation) HW Module Plug-'n'-Play Output port Input port Interface Plug-and-play channels in the link communication model Predefined channel augmented with analytical model

23. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Spice SystemC SystemC vs SPICE accuracy Accuracy results for 30 different mixes of noise sources  Average error at sampling time never worse than 2%, max. error less than 7%  Risk of logic value misprediction if sampled voltage close to decision threshold a warning is generated by the SystemC channel  Accounting for Inter-Symbol Interference  Simulation time improvements with SystemC by 10x

24. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Outline 1.Motivation 2.Physical channel design 3.Analytical model Design Validation against HSPICE 4.Macromodel integration in SystemC Accuracy assessment 5.Applications and conclusions

25. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Communication channel exploration First application Injection of noise in the transmitter until a logic error is produced at the receiver FFTX Power supply noise

26. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Communication channel exploration Second application: Exploration of different clocking schemes Clock TX Clock RX 1000 ps = 1 GHz Native dual clocking schemes with phase shift Which is the min. shift for correct sampling at 1 GHz? SystemC  35ps HSPICE  35ps (exact matching)

27. alessandro.bogliolo@uniurb.it SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Conclusions  Design of a communication channel for high-performance on-chip links  targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes  low power, low swing signaling  Analytical modelling of channel behavior in presence of noise  Noise sensitive area concept, delay and signal slope models  Macromodel integration into SystemC  Powerful communication abstractions  Plug-and-play backannotated channel  Very high accuracy in predicting far-end voltage at sampling time  Average error below 2%, max error below 7%  Improvement of simulation time by 10x  Accounting for Inter-Symbol Interference  Macromodels at work for fast  assessment of channel robustness against noise sources  physical channel design space exploration  Future work: crosstalk analytical macromodelling