Presentation is loading. Please wait.

Presentation is loading. Please wait.

9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends.

Published byLynn Rose Modified over 8 years ago

Similar presentations

Presentation on theme: "9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends."— Presentation transcript:

1 9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends solely on the current input –Sequential logic is defined as that in which the output does depend on previous inputs.

2 9/9/2006DSD,USIT,GGSIPU2 Concurrent statement Operators The WHEN statement –(When/Else or With/select/when) –The GENERATE statement –The BLOCK statement

3 9/9/2006DSD,USIT,GGSIPU3 Operators Most basic way of creating concurrent code. Operators can be used to implement any combinational circuit. Operators –AND, OR, +, -, *, sll, sra, etc

4 9/9/2006DSD,USIT,GGSIPU4 Operators Operator Type OperatorsData types LogicalNOT,AND,NAND, NOR, OR, XOR,XNOR Bit, Bit_vector Std_logic,std_logic_vector Std_ulogic_vector, std_ulogic Arithmetic+, -, *, /, **Integer,signed, unsigned Comparison=,/=,, =All above ShiftSll,srl,sla,sra,rol,rorBit_vector Concatenation&, (,,,)Same as above

5 9/9/2006DSD,USIT,GGSIPU5 When (Simple and selected) Fundamental concurrent statement Syntax assignment WHEN condition ELSE ……….;

6 9/9/2006DSD,USIT,GGSIPU6 Important Aspect of WHEN WHEN value -- Single value WHEN value1 to value2 – Range, for enumerated data types WHEN value1|value2|……… - value1 or value2

7 9/9/2006DSD,USIT,GGSIPU7 Circuit of 2:4 decoder

8 9/9/2006DSD,USIT,GGSIPU8 3:8 Decoder entity decodedr38 is Port ( a : in std_logic_vector(2 downto 0); b : out std_logic_vector(7 downto 0); en : in std_logic); end decodedr38; architecture Behavioral of decodedr38 is signal temp : std_logic_vector(7 downto 0); begin temp <= "00000001" when a="000" else "00000010" when a="001" else "00000100" when a="010" else "00001000" when a="011" else "00010000" when a="100" else "00100000" when a="101" else "01000000" when a="110" else "10000000"; b <= temp when en='1' else (others => '0'); end Behavioral;

9 9/9/2006DSD,USIT,GGSIPU9 5:32 Decoder 5x32 decoder 2:4 3:8

10 9/9/2006DSD,USIT,GGSIPU10 5:32 decoder entity decoder532 is Port ( x : in std_logic_vector(4 downto 0); y : out std_logic_vector(31 downto 0)); end decoder532; architecture Behavioral of decoder532 is component decoder24 is Port ( din : in std_logic_vector(1 downto 0);-- decoder input dout : out std_logic_vector(3 downto 0) );-- decoder output end component decoder24; component decodedr38 is Port ( a : in std_logic_vector(2 downto 0); b : out std_logic_vector(7 downto 0); en : in std_logic); end component decodedr38; signal temp : std_logic_vector(3 downto 0);

11 9/9/2006DSD,USIT,GGSIPU11 5:32 decoder (cont..) begin u1: decoder24 port map(din(1)=>x(4),din(0)=>x(3),dout(3)=>temp(3),dout(2)=>temp(2),dout(1)=>temp(1),dout(0)=>te mp(0)); u2: decodedr38 port map(en=>temp(0),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(7),b(6)=>y(6),b(5)=>y(5),b(4)=>y(4),b (3)=>y(3),b(2)=>y(2),b(1)=>y(1),b(0)=>y(0)); u3: decodedr38 port map(en=>temp(1),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(15),b(6)=>y(14),b(5)=>y(13),b(4)=>y( 12),b(3)=>y(11),b(2)=>y(10),b(1)=>y(9),b(0)=>y(8)); u4: decodedr38 port map(en=>temp(2),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(23),b(6)=>y(22),b(5)=>y(21),b(4)=>y( 20),b(3)=>y(19),b(2)=>y(18),b(1)=>y(17),b(0)=>y(16)); u5: decodedr38 port map(en=>temp(3),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(31),b(6)=>y(30),b(5)=>y(29),b(4)=>y( 28),b(3)=>y(27),b(2)=>y(26),b(1)=>y(25),b(0)=>y(24)); end Behavioral;

12 9/9/2006DSD,USIT,GGSIPU12 Conditional Signal Assignment statement The conditional signal assignment statement selects different values for the target signal based on the specified, possibly different, conditions. A typical syntax – target-signal <= [waveform-elements when condition else [waveform-elements when condition else.. Waveform-elements when condition];

13 9/9/2006DSD,USIT,GGSIPU13 Example 4: 1 Mux using when statement library ieee; use ieee.std_logic_1164.all; entity mux4_1_when is port (a: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); y: out std_logic ); end mux4_1_when; architecture mux_behave of mux4_1_when is begin y <= a(0) when s = "00" else a(1) when s = "01" else a(2) when s = "10" else a(3); end mux_behave;

14 9/9/2006DSD,USIT,GGSIPU14 Symbol of 2:1 Mux

15 9/9/2006DSD,USIT,GGSIPU15 Selected signal Assignment statement The selected signal assignment statement selects different values for a target signal based on the value of a select expression. A typical syntax – With expression select target-signal <= waveform-element when choices, waveform-element when choices,.. waveform-element when choices;

16 9/9/2006DSD,USIT,GGSIPU16 Example 4:1 mux using with- select library ieee; use ieee.std_logic_1164.all; entity mux4_1_with is port (a: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); y: out std_logic ); end mux4_1_with; architecture mux_behave of mux4_1_with is begin with s select y <= a(0) when "00", a(1) when "01", a(2) when "10", a(3) when others; end mux_behave;

17 9/9/2006DSD,USIT,GGSIPU17 Mux architecture

18 9/9/2006DSD,USIT,GGSIPU18 Circuit of Encoder

19 9/9/2006DSD,USIT,GGSIPU19 Truth table of encoder A3`A2A1A0F1F0 000100 001001 010010 100011

20 9/9/2006DSD,USIT,GGSIPU20 7-segment display

21 9/9/2006DSD,USIT,GGSIPU21 InputOutput No.X3X2X1X0GFEDCBA 000000111111 100010000110 200101011011 300111001111 401001100110 501011101101 601101111100 701110000111 810001111111 910011100111 Truth table of 7-segment display decoder

Download ppt "9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends."

Similar presentations

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.
Arbitrary Waveform Discussion 5.5 Example 34.

Arbitrary Waveform Discussion 5.5 Example 34.
1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.
Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Generic Multiplexers: Parameters Discussion D2.5 Example 8.
Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.
Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.
Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.
4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.
1 Part II: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

1 Part II: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
EE 367 – Logic Design Lecture #17

EE 367 – Logic Design Lecture #17
CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.

CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.
Data Flow Modeling of Combinational Logic Simple Testbenches

Data Flow Modeling of Combinational Logic Simple Testbenches
1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.
DSD,USIT,GGSIPU1 Entity declaration –describes the input/output ports of a module entity reg4 is port ( d0, d1, d2, d3, en, clk : in std_logic; q0, q1,

DSD,USIT,GGSIPU1 Entity declaration –describes the input/output ports of a module entity reg4 is port ( d0, d1, d2, d3, en, clk : in std_logic; q0, q1,
CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #17 – Introduction.

CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #17 – Introduction.
ENG241 Digital Design Week #4 Combinational Logic Design.

ENG241 Digital Design Week #4 Combinational Logic Design.

Similar presentations

Ads by Google