1. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 IEEE Standard 1149.6: Boundary-Scan Testing of Advanced Digital Networks J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL Tel. 351 225 081 748 / Fax: 351 225 081 443 (jmf@fe.up.pt / http://www.fe.up.pt/~jmf)

2. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)2 Outline Scope and objectives of 1149.6 AC coupling, differential signalling 1149.6 defect model Testing AC-coupled / differential networks (placement of BS cells, new instructions) 1149.6: test driver and test receiver Conclusion

3. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)3 Scope and objectives Scope of 1149.6: Structural test of high- speed digital networks Objectives –Cope with differential and/or AC-coupled interconnections, enabling high fault coverage with minimum impact on mission logic –Reuse as much as possible IEEE 1149.1 tools (ensure compatibility with 1149.1 / 4)

4. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)4 AC-coupling, differential signalling Single-ended signalling with AC-coupling Differential signalling with AC-coupling and bias provision TX: RX:

5. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)5 1149.6 defect model

6. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)6 1149.6 defect model (cont.)

7. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)7 Testing AC-coupled / differential networks BS cell placement has an impact on circuit performance and defect coverage Modified BS cells must ensure: –Signal transmission over AC-coupled nets –Logic level detection from AC test signals

8. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)8 1149.6 drivers and receivers An AC testing instruction selects the AC Mode, and a test signal suited for AC-coupled networks is applied to the pin A test receiver at the input cell derives logic level information from the incoming AC / DC test signal

9. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)9 1149.6 instructions for AC- coupled differential networks EXTEST_PULSE generates a transition even when the new test value at the driver pin retains its previous value EXTEST_TRAIN provides multiple additional transitions (to cope with transient conditions, when necessary) Both cause the driver pins to change state at least twice in Run-Test / Idle

10. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)10 EXTEST_PULSE

11. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)11 EXTEST_TRAIN

12. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)12 General AC pin driver

13. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)13 The test receiver Extracts test data even in the presence of an unknown offset The solution is to look for valid transitions (with a minimum voltage swing ΔV and a maximum transition time Δt) Single-ended signal reception:

14. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)14 Operation of the test receiver When an AC testing instruction is loaded, the test receiver detects transitions at the input pin and sends the logic level information to the capture / shift stage of the BS cell When the current instruction is EXTEST, the test receiver sends the input logic level to the capture / shift stage of the BS cell

15. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)15 The test receiver : transition detection and offset removal A delay element and an hysteretic comparator –Detect input signal transitions (by comparing a signal with a delayed version of itself) –Provide an output at standard logic levels (removing unknown offsets) In+: In-: Out:

16. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)16 The test receiver (AC Mode / DC Mode test receiver model) Test receiver model supporting AC Mode (AC testing instructions) and DC Mode (EXTEST): or a time-decaying variant: IEEE std 1149.6, p. 27: “two simple comparators, one to sense rising edges and the other to sense falling edges; two V Hyst voltage sources, to set the hysteresis voltage for the comparators; and a D-type flip-flop memory element, to hold the reconstructed signal.”

17. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)17 Test receiver support for AC testing instructions The output of the hysteretic comparator FF will also be as shown when the input signal V in decays over time

18. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)18 Test receiver support for (DC) EXTEST instruction The delay network (RC) is replaced by a bias voltage, since transition detection is no longer required

19. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)19 BS cell with test receiver 1149.6 std 6.2: “When an AC testing instruction is in effect, it is the purpose of the test receiver to reconstruct the test waveform driven by the upstream driver when either AC- or DC-coupling is used. It does this by reacting to the edges and not the levels of the input waveform. When (DC) EXTEST is in effect, the test receiver behaves as a level detector.”

20. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)20 1149.6 std 6.2.2.1-d): “Whenever a test receiver is operating in the level- detection mode on an AC input pin, the test receiver output shall be cleared of prior history on the falling edge of TCK in the Capture-DR TAP Controller state.” 1149.6 std 6.2.2.2-a): “the output of the test receiver is only relevant during the window of time between the falling and rising edges of TCK in the Capture-DR (…) state.” BS cell with test receiver (DC Mode) A valid input (> V bias +V hyst or < V bias – V hyst ) will force the HC FF into Set or Clear; otherwise the Capt. FF state will be retained

21. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)21 Test receiver operation (DC Mode) Valid input: set / clear the HC FF –Set: V in –V hyst > V bias (i.e. V in > V bias +V hyst ) –Clear: V in +V hyst < V bias (i.e. V in < V bias -V hyst ) Invalid input (within the test window): the Capture FF will retain the current value

22. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)22 BS cell with test receiver (AC Mode) Valid transitions will force the HC FF into Set or Clear; if no valid transitions occur, the Capture FF state will be retained 1149.6 std 6.2.3.1-d): “Whenever a test receiver is operating in the edge- detection mode on an AC input signal, the test receiver output shall be cleared of prior history at a time between exiting the Shift-DR TAP controller state and before entering (…) Update-DR (…).”

23. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)23 Test receiver operation (AC Mode) Valid input: set / clear the HC FF Invalid input (within the test window): the Capture FF will retain the current value

24. © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)24 Conclusion Industry-driven 1149.6 enables structural testing capability of AC-coupled single- ended or differential networks An underlying fault model facilitates high defect coverage Compatibility with 1149.1 enables minimal impact on 1149.1 tools