1. AC circuit analysis Procedures to solve a problem –Identify the sinusoidal and note the excitation frequency. –Covert the source(s) to phasor form –Represent each circuit element by its impedance –Solve the resulting phasor circuit using previous learnt analysis tools –Convert the (phasor form) answer to its time domain equivalent. Ex. 4.16, p180

2. Charging a Capacitor 0.63   t v(t) t=RC=  t i  /R t=RC=  0.63  /R Time constant (  ): time needs to charge a capacitor to 63% of its full charge. The larger the RC, the longer it takes to charge a capacitor. The larger the R value, the smaller the current is in the circuit. The larger the C value, the more the charge the capacitor can hold

3. Discharging a Capacitor  i=0 Vc=Vc= ++++ ---- t = 0 i  Vc=Vc= ++++ ---- t v C (t) 

4. Example The flashing lights seen on barricades at street work and construction sites are driven by relaxation oscillator circuits such as the one shown in the figure, with N being a neon lamp. The lamp is nonconducting until the voltage across it (and the capacitor also) rises to a value of 45 V whereupon it "ignites," dropping its resistance almost instantly to zero and discharging the capacitor. Then the lamp again becomes nonconducting and the process repeats. If the emf of the battery is 60 V and C = 0.10 microfarad, what should R be for the lamp to flash every 1.5 sec? R=11 M 

5. The average ac power (P av ) is the power dissipated on the load resistor. 0  cos  1, dependent on the complex load. ideal power factor: cos  =1, Z=R, pure resistive load Exam II Review: AC Power rms value Average power

6. Review cont.: Complex Power real power P av : power absorbed by the load resistance. Q (volt-amperes reactive, VAR): exchange of energy between the source and the reactive part of the load. No net power is gained or lost during the process.  S  : compute by measuring the rms load voltage and currents without regard for the phase angle. if Q 0, the load is inductive Instantaneous power p(t) Pay attention to complex conjugate

7. Topic 2: Digital Circuit: Combinational Logic Logic operation Real problem to truth table Karnaugh Map: –Box “1” or box “0” Largest supercell possible 2 n ones or zeros in each supercell Edges of Karnaugh map are connected Finish all ones or zeros Doesn’t matter (“d” or “x”) can be considered as either “1” or “0”.

8. Digital Circuit Review: Sequential Logic Flip Flips Timing diagram 1.When CLK signal arrives (rising edge or falling edge), FF will have outputs (Q and Q’) depending on the input (ex. D, or J, K). At this stage, ignore combinational logic if there exist in the circuit. 2.After finishing the output (Q and Q’), then work on the combinational logic, which typically determines the inputs (ex. D, or J, K) which will determine the output (Q and Q’) at next CLK signal Sequential circuit design: State Map 1.Construct a state map. 2.Convert the state map to truth map. Note: have to include all combination. Ex. If there are three outputs, Q 0, Q 1, and Q 2, then there are 8 states (combinations) that have to be listed. Some of them may be listed as “d”. 3.Prepare the inputs such that the outputs (Q 0, Q 1, and Q 2 ) at next state will follow the state map. 4.Convert the truth map to Karnaugh map: the inputs of FF (ex, D, or J, K) is the results in Karnuagh map, i.e. the value of the inputs of FF goes into cells. The outputs of FF is the inputs in the Karnaugh map.