1. CEC 220 Digital Circuit Design Timing Analysis of State Machines
Monday, November 9
CEC 220 Digital Circuit Design

2. CEC 220 Digital Circuit Design
Lecture Outline
Analysis from Timing Diagrams
Analysis from sequential circuits
Monday, November 9
CEC 220 Digital Circuit Design

3. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 1. Reverse Engineering from a Timing Diagram
Given the timing diagram for a clocked sequential circuit (i.e., “state machine”) determine the state transition graph
Clock
Input
Output
State
FFA
FFB
How many Flip-Flops?
Rising or falling edge triggered?
Moore or Mealy machine?
Monday, November 9
CEC 220 Digital Circuit Design

4. Timing Analysis of State Machines 1
Timing Analysis of State Machines 1. Reverse Engineering from a Timing Diagram
Clock
Input
Output
State
FFA
FFB 1 1 1 1
x=0
falling edge triggered S1
Z=0
x=1 S0
Z=0
x=1
x=0
Moore Machine S2
Z=1
x=1
x=1
x=0 S3
Z=0
x=0
Is the state machine completely defined?
Let’s assume that S2  S3 if x=0.
Monday, November 9
CEC 220 Digital Circuit Design

5. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 1. Reverse Engineering from a Timing Diagram
Develop the State Transition Table
Present State
Next State
Present Output (Z)
x=0
x=1 S0 S1 S2 S3 S0 S1 S3 S1 S3 S1 1 S0 S2
Present State
Next State
Present Output (Z)
w=0
w=1 00 01 11 10 1
State Encoding
QAQB
S0 = 00
S1 = 01
S2 = 10
S3 = 11
Monday, November 9
CEC 220 Digital Circuit Design

6. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 2. Reverse Engineering from a Circuit
Given the sequential circuit determine the state transition table & graph x
𝐷 𝐴 𝑄 𝐴
𝑄 𝐴 Z
𝐷 𝐵 𝑄 𝐵
𝑄 𝐵
How many states?
Moore or Mealy machine?
Clk
Input Logic
Flip-Flops
Output Logic
Monday, November 9
CEC 220 Digital Circuit Design

7. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 2. Reverse Engineering from a Circuit
Develop the State Transition Table
Could use the FF Excitation Eqns
And go directly to Next State Cols!!
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
X=1
DA DB 00
0 0
0 1 01
1 1 10 1 11
1 0
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
X=1
DA DB 00 01 10 11
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
X=1
DA DB 00 01 10 1 11
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
X=1
DA DB 00 01
0 0
0 1 11
1 1 10 1
1 0
Moore Machine
Four States
Monday, November 9
CEC 220 Digital Circuit Design

8. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 2. Reverse Engineering from a Circuit
Develop the state transition graph
x=0
x=1
S00
Z=0
S01
S11
S10
Z=1
x=1
x=0
x=1
x=0
x=1
x=0
Compare this graph with the one obtained from the prior waveform example.
Monday, November 9
CEC 220 Digital Circuit Design

9. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 3. Reverse Engineering from a Timing Diagram
Given the timing diagram for a clocked sequential circuit (i.e., “state machine”) determine the state transition graph
Clock
Input
Output
State
FFA
FFB
How many Flip-Flops?
Rising or falling edge triggered?
Moore or Mealy machine?
Monday, November 9
CEC 220 Digital Circuit Design

10. Timing Analysis of State Machines 3
Timing Analysis of State Machines 3. Reverse Engineering from a Timing Diagram
Clock
Input
Output
State
FFA
FFB 1 1 1 1
x=0 /
falling edge triggered S0 S1
x=1 /
x=0 /
Mealy Machine
x=1 /
x=1 / 1 S2
x=0 /
Monday, November 9
CEC 220 Digital Circuit Design

11. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 3. Reverse Engineering from a Timing Diagram
Develop the State Transition Table
Present State
Next State
Present Output (Z)
X=0
X=1 S0 S1 S2 S0 S1 S2 S1 S0 S1 1
Present State
Next State
Present Output (Z)
X=0
X=1 00 01 10 1 11 XX X
Present State
Next State
Present Output (Z)
X=0
X=1 00 01 10 1 11 X
State Encoding
QAQB
S0 = 00
S1 = 01
S2 = 10
Monday, November 9
CEC 220 Digital Circuit Design

12. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 4. Reverse Engineering from a Circuit
Given the sequential circuit determine the state transition table & graph
𝐷 𝐴 𝑄 𝐴
𝑄 𝐴
𝐷 𝐵 𝑄 𝐵
𝑄 𝐵
Clk Z x
How many states?
Moore or Mealy machine?
Input Logic
Flip-Flops
Output Logic
Monday, November 9
CEC 220 Digital Circuit Design

13. CEC 220 Digital Circuit Design
Timing Analysis of State Machines 4. Reverse Engineering from a Circuit
Could use the FF Excitation Eqns
And go directly to Next State Cols!!
Develop the State Transition Table
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
(𝑸 𝑨 + 𝑸 𝑩 + )
X=1
DA DB 00 01 10 1 11
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
(𝑸 𝑨 + 𝑸 𝑩 + )
X=1
DA DB 00 01 10 11
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
(𝑸 𝑨 + 𝑸 𝑩 + )
X=1
DA DB 00
0 0
0 1 01
1 0 10 1 11
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
Flip-Flop Inputs
X=0
(𝑸 𝑨 + 𝑸 𝑩 + )
X=1
DA DB 00
0 0
0 1 01
1 0 10 1 11
Mealy Machine
Four States
Monday, November 9
CEC 220 Digital Circuit Design

14. Develop the state transition graph
Timing Analysis of State Machines 4. Reverse Engineering from a Circuit
If we start at S00, S01, or S10 we will never reach S11
Develop the state transition graph
x=0 / 0
Present State
𝑸 𝑨 𝑸 𝑩
Next State
Present Output (Z)
X=0
(𝑸 𝑨 + 𝑸 𝑩 + )
X=1 00
0 0
0 1 01
1 0 10 1 11
S00
x=0 /
x=1 / 0
x=1 / 0
x=1 / 1
S01
S10
x=0 / 0
x=0 / 0
x=1 /1
Compare this graph with the one obtained from the prior waveform example.
S11
We can effectively ignore S11
Monday, November 9
CEC 220 Digital Circuit Design

15. CEC 220 Digital Circuit Design
Timing Analysis of State Machines Method#1: VHDL Code to generate these Examples
Moore State Machine:
Cases 1 & 2
Mealy State Machine:
Cases 3 & 4
See course webpage for VHDL code
Monday, November 9
CEC 220 Digital Circuit Design

16. CEC 220 Digital Circuit Design
Timing Analysis of State Machines Method#2: VHDL Code to generate these Examples
Moore State Machine:
Mealy State Machine:
See course webpage for VHDL code
Monday, November 9
CEC 220 Digital Circuit Design

17. CEC 220 Digital Circuit Design
Next Lecture
Sequence Detector design
Monday, November 9
CEC 220 Digital Circuit Design