1. Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. 22004/05/24Analysis of Clocked Sequential Circuits Outline 13.1A Sequential Parity Checker 13.2Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits

3. 32004/05/24Analysis of Clocked Sequential Circuits A Sequential Parity Checker A parity bit An extra bit An extra bit Being added for purposes of error detection Being added for purposes of error detection Odd parity Total number of 1 bits is odd Total number of 1 bits is odd Even parity Total number of 1 bits is even Total number of 1 bits is even

4. 42004/05/24Analysis of Clocked Sequential Circuits A Sequential Parity Checker A parity checker for serial data The data enters the circuit sequentially, one bit a time The data enters the circuit sequentially, one bit a time

5. 52004/05/24Analysis of Clocked Sequential Circuits A Sequential Parity Checker A parity checker for serial data The data enters the circuit sequentially, one bit a time The data enters the circuit sequentially, one bit a time Z = 1 If the total number of 1 inputs received is odd If the total number of 1 inputs received is odd Z = 0 If the total number of 1 inputs received is even If the total number of 1 inputs received is even An error occurs Data with odd parity Data with odd parity Final output of Z = 0 Final output of Z = 0

6. 62004/05/24Analysis of Clocked Sequential Circuits A Sequential Parity Checker The clock input To distinguish consecutive 0’s or consecutive 1’s on the X input To distinguish consecutive 0’s or consecutive 1’s on the X input

7. 72004/05/24Analysis of Clocked Sequential Circuits State Graph for Parity Checker Two states are required S 0 S 0 an even number of 1’s received an even number of 1’s received S 1 S 1 an odd number of 1’s received an odd number of 1’s received

8. 82004/05/24Analysis of Clocked Sequential Circuits State Table for Parity Checker

9. 92004/05/24Analysis of Clocked Sequential Circuits Parity Checker

10. 102004/05/24Analysis of Clocked Sequential Circuits Outline 13.1A Sequential Parity Checker 13.2Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits

11. 112004/05/24Analysis of Clocked Sequential Circuits Basic Procedure 1.Assume an initial state of the flip-flops (all flip- flops reset to 0 unless otherwise specified). 2.For the first input in the given sequence, determine the circuit output(s) and flip-flop inputs. 3.Determine the new set of flip-flop states after the next active clock edge. 4.Determine the output(s) that corresponds to the new states. 5.Repeat 2,3, and 4 for each input in the given sequence.

12. 122004/05/24Analysis of Clocked Sequential Circuits Two Types of Clocked Sequential Circuits Moore machine the output of a sequential circuits is a function of the present state only the output of a sequential circuits is a function of the present state only Mealy machine the output is a function of both the present state and the input the output is a function of both the present state and the input

13. 132004/05/24Analysis of Clocked Sequential Circuits Moore and Mealy State Graphs Moore Mealy

14. 142004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit Z is a function only of the present state Z = A  B Z = A  B

15. 152004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit Initially X = 0, A = B = 0 X = 0, A = B = 0 00 00 01

16. 162004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit Initially X = 0, A = B = 0 X = 0, A = B = 0 0 0 00 01 10 0

17. 172004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit After the first active clock A = 1, B = 0, X = 1 A = 1, B = 0, X = 1 1 1 10 11 10 0

18. 182004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit After the first active clock Z =1, X = 1 Z =1, X = 1 1 1 10 11 01 1

19. 192004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit After the second active clock A = 0, B = 1 A = 0, B = 1 1 1 01 00 01 1

20. 202004/05/24Analysis of Clocked Sequential Circuits Moore Sequential Circuit After the second active clock Z = 1, X = 1 Z = 1, X = 1 1 1 01 00 11 1

21. 212004/05/24Analysis of Clocked Sequential Circuits Timing Chart

22. 222004/05/24Analysis of Clocked Sequential Circuits Timing Chart Initial output Z = 0 could be ignored Not in response to any X input Not in response to any X input The output is displaced in time with respect to the input sequence. X = 0 1 1 0 1 A = 0 1 0 1 0 1 B = 0 0 1 1 1 1 1 Z = (0) 1 1 0 1 0

23. 232004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit

24. 242004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit The output depends on both the input (X) and the flip-flops states (A and B), so Z may change either when the input changes or when the flip-flops change state.

25. 252004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit Initially 00 11 1 1 1 1100 11

26. 262004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit Initially 00 11 1 1 1 1 1100 00 11

27. 272004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit First active clock 01 1->0 0 0 1 10 00 01 1 1 0->1

28. 282004/05/24Analysis of Clocked Sequential Circuits Mealy Sequential Circuit First active clock 01 1->0 0 0 0->1 1->0 10 00 01 1 1 0->1 00

29. 292004/05/24Analysis of Clocked Sequential Circuits Timing Chart

30. 302004/05/24Analysis of Clocked Sequential Circuits False Outputs After the circuit has changed state and before the input is changed, the output may temporarily assume an incorrect value. After the circuit has changed state and before the input is changed, the output may temporarily assume an incorrect value. Also called glitches and spikes Also called glitches and spikes X = 1 0 1 0 1. A = 0 0 0 1 1 0 B = 0 1 1 1 1 0 Z = 1(0) 1 0(1) 0 1