1. Andrei Nomerotski 1 3D ISIS : Different approach to ISIS Andrei Nomerotski, LCFI Collaboration Meeting Bristol, 20 June 2006 Outline  What is 3D ? u Reviewed by Ray Yarema’s in Ringberg May 2006, see http://www.hll.mpg.de/~lca/ringberg/, three Ray’s slides will followhttp://www.hll.mpg.de/~lca/ringberg/  3D ISIS – some ideas to merge ISIS and 3D approaches  Some speculations about future (not much)

2. Andrei Nomerotski 2 Introduces multilayer PCB philosophy into silicon planar technologies

3. Andrei Nomerotski 3

4. 4 (by MIT Lincoln Labs)

5. Andrei Nomerotski 5 3D ISIS Concept  How 3D can help ISIS?  Difficulties of classical ISIS u CCD and CMOS process on same wafer u Complex topology of CCD gates for linear structures 3D ISIS has two Tiers  1 st Tier : Storage (CCD) part  2 nd Tier : Readout (CMOS) part

6. Andrei Nomerotski 6 3D ISIS Imaging Pixel  View from above   Store charge in a linear zigzagged CCD register u Need two phase design u As shown has 7 cells – more complicated designs possible  CCD register is confined to a single cell  Simplified gate structure a la’ CPCCD u Charge is moved in all cells simultaneously  Has a via to 2 nd Tier – used for readout phase Advantages:  1 st Tier is purely CCD process, 2 nd Tier is purely CMOS process  As there are no readout components in Tier 1, more room is left for storage cells and photo-gate, assumed 5x15 um PhG, 3 um cells, 3um via – nothing pushes technology

7. Andrei Nomerotski 7 3D ISIS Clock Steering  Simplified (wrt ISIS) clock steering : whole sensor is driven simultaneously  What about driving large capacitive load i.e. CPCCD-like problems?    Need to move charge 20 times in 1 ms = 20 kHz instead of 50 MHz as in CPCCD  easier to drive  Clock should be fast enough to move the charge before next bunch crossing (330 ns)  5 MHz  Less area occupied by gates = lower C  Considerably less transfers wrt CPCCD (20 vs 5000) = care less about CTE

8. Andrei Nomerotski 8 3D ISIS Readout  During readout CCD register is advanced and charge appears in 2 nd Tier through the via simultaneously for all pixels – similar to MAPS, FAPS, SOI.  Column-based readout : have 200 ms per 5000 pixels – 40 us/pixel which is a lot of time. Many approaches possible, ex. a la’ ATLAS. Advantages  Simple (compared to FAPS etc) design : storage capacity is implemented in 1 st Tier  Clock manipulations are minimal during readout (just advancing the CCD register), can be done externally without introducing extra connections between Tiers 1 and 2 (no edge logic necessary in Tier 1)

9. Andrei Nomerotski 9 3D ISIS Open Issues As any new idea 3D ISIS has many open issues – just to list a few:  Nobody tried so far to bond a CCD wafer to a CMOS wafer - is CCD process compatible with 3D bonding? u Can gate structures be made planar enough? Can aplanarity be compensated by additional CVD oxide & polishing? u Some bonding and via techniques require high T (~450 C) – is it compatible with polySi gates?  Is charge transfer between large photogate and first cell efficient?  Large size of CMOS chip (Tier 2) – yield problems?

10. Andrei Nomerotski 10 Possible Developments  Fermilab has a strong R&D program on SOI pixels based on 3D u Exploring all parts of 3D technologies (wafer bonding, thinning, inter-wafer vias), working with American vendors (MIT LL, Americal Semicondutor, Ziptronix, IZM, RTI), will have 3D multiproject run in 2006 u Design of readout for SOI pixels  We could have Tier 1 ISIS prototypes compatible with their readout and participate in the multiproject run  Some European efforts exist (Belfast QU, Poland, INFN) on 3D and SOI technologies

11. Andrei Nomerotski 11 Summary  Proposed new option for ISIS storage pixels : 3D ISIS u Takes advantage of recent developments in 3D technologies u Opens new opportunities at expense (of course!) of investment needed to explore these new opportunities  It’s clear that to go beyond talking this approach needs 1) A practical design worked out in enough detail 2) Some R&D plan – probably joining forces with existing 3D efforts  Goal of this talk was to distribute this idea more broadly and stimulate some discussion re this direction