1. © 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Adding Your Own IP to the OPB Bus

2. © 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Describe the basic OPB bus transactions Differentiate between free- and evaluation-based IP delivered in the EDK Identify the requirements for integrating your IP List the steps involved in creating and importing peripherals using Create/Import IP wizard Identify the limitations of creating peripherals with the wizard

3. © 2005 Xilinx, Inc. All Rights Reserved Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in the EDK Create and Import Peripheral Wizard

4. © 2005 Xilinx, Inc. All Rights Reserved Overview Peripherals are connected to the microprocessor by using the data and address buses Xilinx has implemented the IBM CoreConnect bus architecture On-Chip Peripheral Bus (OPB) version 2.1 of the CoreConnect bus architecture is designed for easy connection of on-chip peripheral devices Any custom peripheral that connects to the OPB bus must do the following: – Meet the principles of the OPB protocol – Meet the requirements of the Platform Generator This allows you to take advantage of the simple automated flow that generates system-level architecture

5. © 2005 Xilinx, Inc. All Rights Reserved Features Platform Generator supports the following features of the OPB v2.1 for OPB peripherals: – Fully synchronous single-clock edge – 32-bit address bus, 32-bit data bus – Single-cycle transfer of data between the OPB master and the OPB slave – Supports master byte enables – Supports slave timeout suppress – Supports slave retry – No 3-state drivers required Note that the dynamic bus sizing feature is not supported

6. © 2005 Xilinx, Inc. All Rights Reserved Features MicroBlaze™ processor-embedded system

7. © 2005 Xilinx, Inc. All Rights Reserved Physical Implementation The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or other existing peripherals

8. © 2005 Xilinx, Inc. All Rights Reserved Interface Signals Global OPB slave signals – Slave signals _xferAck _errAck _toutSup _retry _DBus – OPB bus signals OPB_select OPB_RNW OPB_BE OPB_seqAddr OPB_Abus OPB_DBus OPB Slave OPB Bus Logic _xferAck _errAck _toutSup _retry _DBus OPB_select OPB_RNW OPB_BE OPB_seqAddr OPB_ABus OPB_DBus

9. © 2005 Xilinx, Inc. All Rights Reserved Timing Diagram (Read) The OPB master asserts OPB_select and puts valid OPB_ABus, OPB_BE, and OPB_RNW on the buses The slave completes the transfer by asserting OPB_xferAck, which causes the master to latch data from the data bus on read transfers and de-assert OPB_select _xferAck _DBus OPB_BE OPB_RNW OPB_ABus OPB_select OPB_CLK Cycles Valid Address Read Valid BE Valid Data 123456 0000-0000

10. © 2005 Xilinx, Inc. All Rights Reserved Timing Diagram (Write) The OPB master asserts OPB_select and puts valid OPB_ABus, OPB_BE, OPB_RNW, and OPB_DBus on the buses The slave latches the data and completes the transfer by asserting OPB_xferAck, which causes the master to de-assert OPB_select _xferAck OPB_DBus OPB_BE OPB_RNW OPB_ABus OPB_select OPB_CLK Cycles Valid Address Write Valid BE Valid Data 123456 0000-0000

11. © 2005 Xilinx, Inc. All Rights Reserved Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in the EDK Create and Import Peripheral Wizard

12. © 2005 Xilinx, Inc. All Rights Reserved Platform Generator searches the following directories for IP: – pcores directory (located in the project directory) – MyProcessorIPLib directory (user defined) Repository Directory listed using Project  Project Options  Device and Repository tab – $XILINX_EDK/EDK/hw/XilinxProcessorIPLib/pcores (UNIX) – %XILINX_EDK%\EDK\hw\XilinxProcessorIPLib\pcores (PC) XPS Directory Structure simmodels Project Directory pcores hdlnetlist data verilogvhdl MyProcessorIPLib MPDBBD PAO

13. © 2005 Xilinx, Inc. All Rights Reserved Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in the EDK Create and Import Peripheral Wizard

14. © 2005 Xilinx, Inc. All Rights Reserved Simulation Generator Hardware Platform Generation Library Generation Embedded Software Development ISE Tools IP Library or User Repository MSS LibGen.a Compiler (GCC).o Linker (GCC) ELF MHS PlatGen Drivers, MDD MPD, PAO PCore HDL System and Wrapper VHD system.BMM Synthesis (XST) NGC NGDBuildUCF NGD MAP NCD, PCF PAR NCD BitGensystem.BIT BitInit download.BIT iMPACT system_BD.BMM SimGen Behavioral VHD Model SimGen Structural VHD Model SimGen Timing VHD Model Simulation IP ModelsISE Models Testbench Stimulus CompEDKLibCompXLib Application Source.c,.h,.s MPD, PAO, BBD download.CMD EDK SW Libraries

15. © 2005 Xilinx, Inc. All Rights Reserved MPD File ## MPD file created automatically for design OPB_SEMAPHORE BEGIN opb_pwm, IPTYPE=PERIPHERAL ## Parameter list for the generics PARAMETER C_OPB_AWIDTH = 32, DT = integer PARAMETER C_OPB_DWIDTH = 32, DT = integer PARAMETER C_BASEADDR = 0xFFFF8000, DT = std_logic_vector PARAMETER C_HIGHADDR = 0xFFFF80FF, DT = std_logic_vector PARAMETER C_NO_CHANNELS = 4, DT = integer PARAMETER C_MAX_RESOLUTION = 16, DT = integer OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE entity OPB_PWM is generic ( C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFA000"; C_HIGHADDR : std_logic_vector := X"FFFFA0FF"; C_NO_CHANNELS : integer range 0 to 15 := 4; C_MAX_RESOLUTION : integer range 4 to 32 := 16 ); Parameters override generics in VHDL

16. © 2005 Xilinx, Inc. All Rights Reserved ## Port list for the signals ## Global signals PORT OPB_Clk = "", DIR = in, SIGIS=CLK, BUS=SOPB PORT OPB_Rst = OPB_Rst, DIR = in, BUS=SOPB ## OPB signals PORT OPB_ABus = OPB_ABus, DIR = in, VEC = [0:31], BUS=SOPB PORT OPB_BE = OPB_BE, DIR = in, VEC = [0:3], BUS=SOPB PORT OPB_RNW = OPB_RNW, DIR = in, BUS=SOPB PORT OPB_select = OPB_select, DIR = in, BUS=SOPB PORT OPB_seqAddr = OPB_seqAddr, DIR = in, BUS=SOPB PORT OPB_DBus = OPB_DBus, DIR = in, VEC = [0:31], BUS=SOPB PORT PWM_DBus = Sl_DBus, DIR = out, VEC = [0:31], BUS=SOPB PORT PWM_errAck = Sl_errAck, DIR = out, BUS=SOPB PORT PWM_retry = Sl_retry, DIR = out, BUS=SOPB PORT PWM_toutSup = Sl_toutSup, DIR = out, BUS=SOPB PORT PWM_xferAck = Sl_xferAck, DIR = out, BUS=SOPB PORT PWM = "", DIR = out, VEC = [0:C_NO_CHANNELS-1] END MPD File port ( -- Global signals OPB_Clk : in std_logic; OPB_Rst : in std_logic; -- OPB signals OPB_ABus : in std_logic_vector(0 to 31); OPB_BE : in std_logic_vector(0 to 3); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; OPB_DBus : in std_logic_vector(0 to 31); OPB Bus Signals PWM_DBus : out std_logic_vector(0 to 31); PWM_errAck : out std_logic; PWM_retry : out std_logic; PWM_toutSup : out std_logic; PWM_xferAck : out std_logic; PWM : out std_logic_vector(0 to C_NO_CHANNELS-1) ); Slave Signals

17. © 2005 Xilinx, Inc. All Rights Reserved PAO File ############################################################################## ## Filename: R:\training\embedded\lab1/pcores/lcd_v1_00_a/data/lcd_v2_1_0.pao ## Description: Peripheral Analysis Order lib proc_common_v1_00_b proc_common_pkg vhdl lib proc_common_v1_00_b direct_path_cntr vhdl lib proc_common_v1_00_b srl_fifo vhdl lib proc_common_v1_00_b srl_fifo_rbu vhdl lib proc_common_v1_00_b pselect vhdl lib proc_common_v1_00_b ld_arith_reg vhdl lib proc_common_v1_00_b ld_arith_reg2 vhdl … # --USER-- add all user core source files and change the following source to # your top-level core name and library lib opb_ipif_v2_00_h master_attachment vhdl lib opb_ipif_v2_00_h opb_ipif vhdl lib lcd_v1_00_a user_logic vhdl lib lcd_v1_00_a lcd vhdl Update this section Order of dependency

18. © 2005 Xilinx, Inc. All Rights Reserved BBD File The Black Box Definition (BBD) file identifies files used for a user peripheral The NGC netlists are copied into the project/implementation directory Example of a single file without options: – FILES – Blackbox.ngc Example of multiple file selections without options: – FILES – blackbox1.ngc, blackbox2.ngc, blackbox3.edn

19. © 2005 Xilinx, Inc. All Rights Reserved Example of a BBD File with multiple file selections C_FAMILYC_RPMC_FPU_TYP E FILES virtex2truefullopb_fpu_full.edf virtex2trueliteopb_fpu_lite.edf virtex2ptruefullopb_fpu_full.edf virtex2ptrueliteopb_fpu_lite.edf virtexfalsefullopb_fpu_full_noram32x1d.edf, ram32x1ds.edf virtexfalseliteopb_fpu_lite_noram32x1d.edf, ram32x1ds.edf

20. © 2005 Xilinx, Inc. All Rights Reserved File Usage Two ways to integrate your own IP into XPS: – As a black box Synthesized with XST or a third-party synthesis tool Requires MPD and BBD files – As a source Synthesized with the rest of the processor system Uses XST Requires MPD and PAO files

21. © 2005 Xilinx, Inc. All Rights Reserved Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in the EDK Create and Import Peripheral Wizard

22. © 2005 Xilinx, Inc. All Rights Reserved IP Peripherals Xilinx has created a wide variety of IP cores: – Bus infrastructure cores PLB2OPB bridge PLB – Memory interface cores PLB block RAM PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) controller – Peripherals OPB Serial Peripheral Interface (SPI) Ethernet Media Access Controller (EMAC) – User core template OPB slave attachment OPB master attachment

23. © 2005 Xilinx, Inc. All Rights Reserved Free Cores Included as VHDL Source with EDK Busfsl, lmbopbdcr, ocm, plb, fcb Bus Bridgeopb2opb, opb2dcr, opb2plbfcb2fsl, plb2opb Communicationopb_spihard_temac, plb_temac Debugicon, iba, ila, vio, mdmIba, jtagppc_cntlr GPIOopb_gpioplb_gpio Interrupt Controlleropb_intcdcr_intc Memory Controllermch_opb_ddr, mch_opb_sdram, opb_bram, opb_ddr, opb_emc, opb_sdram, opb_sysace dsbram, isbram, pb_ddr, plb_emc, plb_sdram Timerfit_timer, opb_timer, opb_timebase_wdt Utilitybus_split, flipflop, reduced_logic, vector_logic

24. © 2005 Xilinx, Inc. All Rights Reserved IP Cores Included as Evaluation – OPB UART-16550 – OPB HDLC – OPB IIC – OPB Ethernet 10/100 MAC and Ethernet-Lite 10/100 MAC – OPB ATM Master Utopia Level 2 – OPB ATM Slave Utopia Level 2 – OPB PCI 32 Bridge – OPB ATM Master Utopia Level 3 – OPB ATM Slave Utopia Level 3 – PLB ATM Master Utopia Level 2 – PLB ATM Slave Utopia Level 2 – PLB Ethernet – PLB RapidIO The Evaluation IP installs with a 90-day evaluation license Xilinx developed, delivered, and supported

25. © 2005 Xilinx, Inc. All Rights Reserved Core Sizes The size of each core is available in the data sheet For example, the opb_ethernetlite_v1_01_b data sheet contains the following table:

26. © 2005 Xilinx, Inc. All Rights Reserved Processor System Size The Processor IP Calculator is an online tool that helps you easily estimate the processor IP core size usage www.xilinx.com/ipcenter/ processor_central/ppcip/calc. htm Try it out!

27. © 2005 Xilinx, Inc. All Rights Reserved Outline OPB Bus XPS Directory Structure File Creation: MPD, PAO, BBD IP Delivery in the EDK Create and Import Peripheral Wizard

28. © 2005 Xilinx, Inc. All Rights Reserved Create and Import Peripheral Wizard The wizard helps you create your own peripheral and then import it into your design The wizard generates the necessary core description files into the user-selected directory You can start the wizard after creating a new project or opening an existing project in XPS The user peripheral can be imported directly through the wizard by skipping the creation option – Ensure that the peripheral complies with Xilinx implementation of the IBM CoreConnect bus architecture standard

29. © 2005 Xilinx, Inc. All Rights Reserved Starting the IP Wizard The Create and Import Peripheral Wizard can be started after creating a project and using Hardware  Create or Import Peripheral … or opening an existing project or using Start  Programs  Xilinx Platform Studio 8.1i  Accessories  Create and Import Peripheral Wizard

30. © 2005 Xilinx, Inc. All Rights Reserved Creating a Peripheral Select the target directory – project directory or user repository Select the target directory – project directory or user repository 2 Select Create Peripheral flow 1 The project directory assigned as the target directory will allow the peripheral to be available to the project without importing it. User repository will allow multiple projects to access the same peripheral by importing it in a project

31. © 2005 Xilinx, Inc. All Rights Reserved Selecting a Peripheral Name and Bus Provide the peripheral name and version Provide the peripheral name and version 3 Select the bus to which the peripheral will attach 4

32. © 2005 Xilinx, Inc. All Rights Reserved Selecting Various Functionalities Select the number of interrupts if the interrupt mechanism is selected Select the number of interrupts if the interrupt mechanism is selected 6 Select the functionality 5

33. © 2005 Xilinx, Inc. All Rights Reserved Selecting Software Registers and Address Ranges Select the number of software registers and their widths if the option is selected Select the number of software registers and their widths if the option is selected 7 Select the number of address ranges and their widths if the option is selected 8

34. © 2005 Xilinx, Inc. All Rights Reserved Selecting Additional Signals and ISE Project Generation Optional Bus Functional Model Simulation template 10 Select the additional signals if the peripheral requires it Select the additional signals if the peripheral requires it 9

35. © 2005 Xilinx, Inc. All Rights Reserved Selecting Additional Signals and ISE Project Generation Finish 12 Optional Implementation Tools support 11 Since the project directory was assigned as the target directory the peripheral will appear in the IP Catalog under Project Repository folder

36. © 2005 Xilinx, Inc. All Rights Reserved Importing a Peripheral Select Import Peripheral flow Identify the Repository Directory 12

37. © 2005 Xilinx, Inc. All Rights Reserved Custom IP Name and Source The name of the peripheral must match the top-level entity name or module name The user version name is optional Source file types can be a combination of HDL sources, netlists, and documentation files The top-level HDL must conform to the CoreConnect bus architecture standard Select HDL Source files 4 Enter the top entity name and version name 3

38. © 2005 Xilinx, Inc. All Rights Reserved Custom IP HDL and Location The HDL language can be VHDL or Verilog Source files can already be in a project Source files can be browsed Select the libraries and source files in order of dependency, from lowest to highest Select HDL source files and libraries 6 Select language and browse to source files 5

39. © 2005 Xilinx, Inc. All Rights Reserved Bus Interface If CoreConnect bus architecture naming conventions are followed, the ports are matched; if not, you must assign them Verify that all ports are connected properly 8 Select bus interface 7

40. © 2005 Xilinx, Inc. All Rights Reserved Interrupt Source Select source and any type of interrupt Select source and any type of interrupt 10 Verify the bus information 9 Select interrupting signal source, type (level versus edge), and polarity This will be presented only if interrupt present

41. © 2005 Xilinx, Inc. All Rights Reserved Attributes Select port attributes and change the values Select port attributes and change the values 12 Select parameter attributes and change the values 11 The parameters are listed View or change the parameter default values The changed value is reflected in the MPD file The ports area is listed View or change the parameter default values The changed value is reflected in the MPD file

42. © 2005 Xilinx, Inc. All Rights Reserved Generating Custom IP If the netlist and documentation files were selected earlier, the corresponding GUI displays, requesting their locations If not, the Finished GUI displays If the save box is checked, the previously generated files will also be saved The peripheral will appear under the Peripheral or Project Repository folder in the IP Catalog

43. © 2005 Xilinx, Inc. All Rights Reserved Knowledge Check What is the process for creating a peripheral of custom IP in XPS? What is the process for importing a piece of custom IP into XPS? If you are using a third-party synthesis tool to compile your IP, what files are required to integrate that IP into XPS?

44. © 2005 Xilinx, Inc. All Rights Reserved Answers What is the process for creating a peripheral of custom IP in XPS? – Start the Create and Import Wizard tool from XPS – Select the Create templates for a new peripheral option – Identify the destination directory location – Select the bus interface – Select functionality and any interrupts – Define any software registers and address ranges – Add additional signals which the peripheral may be using – Generate the files – Add user logic in user_logic.vhd

45. © 2005 Xilinx, Inc. All Rights Reserved Answers What is the process for incorporating a piece of custom IP into XPS? – Develop your custom IP by using any combination of HDL, netlist, or libraries Ensure that the top-level file conforms to CoreConnect bus architecture requirements – Start the Create and Import Wizard tool from XPS – Identify the location of libraries, netlists, and source files in order of dependency – Select the bus interface – Select the source and any type of interrupt If you are using a third-party synthesis tool to compile your IP, what files are required to integrate that IP into XPS? – MPD and BBD files

46. © 2005 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Tool documentation – Processor IP Reference Guide – Embedded System Tools Guide  Create/Import Peripheral Wizard – Embedded System Tools Guide  Microprocessor Peripheral Description – Embedded System Tools Guide  Peripheral Analyze Order – Xilinx Drivers Support Website – EDK Website: www.xilinx.com/edk