1. A 128-channel event-driven readout ASIC for the R 3 B Tracker TWEPP 2015, Lisbon Lawrence Jones ASIC Design Group Science and Technology Facilities Council Rutherford Appleton Laboratory

2. Superconducting Fragment Separator (Super-FRS) at FAIR, GSI High-energy branch Nuclear reactions using high-energy radioactive beams. Introduction

3. R 3 B Experiment Reactions with Relativistic Radioactive Beams - R 3 B Target recoil detector measures light charged particles and gamma rays Silicon Tracker surrounds the target together with CALIFA calorimeter

4. R 3 B silicon tracker Silicon microstrip sensor Dual-sided silicon strip sensors Consists of 3 layers 120,000 channels 100 micron thickness for the inner layer and 300 micron thickness for the two outer layers. Introduction R 3 B ASICs

5. Detector Geometry  50um pitch  Double-sided (n & p) stereoscopic strips  Strip length varies depending on position  Capacitance – few pF to 80pF  Data rate – Dependent on position in detector. Worst case: 5kHz/channel  Occupancy – Dependent on position in detector. Worst case: 15%  ASICs on p side at high voltage

6.  Proton rate is ~100s of Hz  Delta electron (background) rate ~100s of kHz (some reactions)  Worst case count rate limited by ADC occupancy  Califa calorimeter will see the protons but not the electrons  Califa produces a “proton detected” validation signal to the ASIC  Tells ASIC to only buffer events when validation is high  The front end must cope with the100kHz electron rate even if the data is not read out  The front end must also recover from 1GeV signals caused by beam misalignment  High dynamic range 50MeV (2V), low threshold 100keV (2mV)  Transistor mismatch Challenges

7. Specification Functional 128 Channels Detector capacitance: up to 80pF Signal polarity: selectable Energy range (silicon strips): 50MeV DC input coupling Leakage current compensation: up to 100nA Selectable shaping time: 0.5  s – 8  s Noise: ~7keV + 0.15keV/pF (RMS) at 2us shaping Data Driven readout ADC: 12 bit SAR, ~1 Msample/s Nearest neighbours Input Clock Frequency: 100MHz or 200MHz Daisy chainable (50MHz) Manchester coded output (selectable) 15 bit Timestamp (5ns or 10ns) On-chip bandgap and DACs for bias generation Power consumption: 7mW /Channel Power supply: 3.3V Physical Process: AMS 0.35um CMOS Size: 12.9mm x 6.2mm

8. R 3 B ASIC Block Diagram Energy Timestamp Channel Readout Daisy Chain Readout Interface & Registers Test Pulse Circuit

9. PreampsShapersx10 amps Comps PH Test Channel logic ADCI2CI2C Control Logic Bandgap & Bias DACs R 3 B ASIC Layout

10. Preamplifier  Detector DC coupled, capacitance up to 80pF  Two feedback circuits, one for leakage current compensation up to 100n. Either can be powered down  Programmable compensation to minimise the rise time and keep the amplifier stable over the different strip capacitance  Range 50MeV (silicon strips)  Pulsed reset, to recover from delta electrons  Switchable polarity feedback  Programmable bias between 0.5V and 2.5V  Overload recovery for 1GeV signals.  Trimmable bias to feedback to compensate for mismatches in the preamp Electrons mode

11. 380k Shaper  Differential amplifier  CR-RC  Bias programmable between 0.5V and 2.5V  Pulsed reset  Programmable shaping time between 0.5us and 8us (4 bit)

12. 12 x10 Amplifier  Low threshold requires gain before comparators  Differential amplifier  Gain set by capacitors  Large value resistive feedback to avoid drift when no signals  Bias programmable between 0.5V and 2.5V  Pulsed reset

13. Peak Hold  Dual polarity peak hold circuit  One amp used as buffer  Common capacitor to save space

14. Peak Hold (holes mode)  One amp used in peak hold circuit  Other amp used as buffer  Trickle current keeps circuit biased when there is no signal to avoid it drifting due to leakage currents  Trickle current removed when a signal occurs

15. Preamp Preamp Reset Shaper Shaper Reset Peak Hold Hit Sample Peak Hold Reset Analog Mux Out PH Sample Simulation of analogue data path

16. Timing  Programmable sample time to account for shaping time  Programmable Peak hold reset length (also resets digital)  Preamp and shaper have fixed length resets

17. 12 bit successive approximation ADC  4 MSBs from resistor string  8 LSBs from capacitor array  Runs at  1 Msample/s  Variable clock period Comparator Input ADC DV RUN CLK

18. Channel Control Logic  Detects Hits and sequences sampling of data. Runs at 1Mhz clock  Controls the resetting of the analogue channels  Reads out data stored in channels to ADC and FIFO  Generate an OR of all hits which can be transmitted off chip as a trigger Chip Control Logic  Generates clocks  Reads out ADC and FIFO  Shifts data off-chip  Controls daisy chaining

19. Daisy Chain  One chip is Master - can generate 50MHz clock  All DAV (data available) signal are ORed as they pass down chain  REN (readout enable) signals stay high until sequence complete  Master finishes the readout cycle once the REN signal returns from the end  Data can be Manchester Coded to allow for capacitive coupling from HV domain  Programmable number of data packets per chip (0- 255) Binary MC CLK 50MHz Master MC output

20. Data Format  Start bits “11”  10 bit chip address  7 bit channel address  15 bit timestamp  12 bit ADC data  1 bit hit status  Stop bit “0”

21. Timestamp correction  If Hit Bit =1 - Indicates the timestamp comparator has fired  If Hit Bit = 0 - Indicates the timestamp comparator has not fired  In this case the timestamp is generated by the slower energy comparator and needs correcting  Timestamp threshold has to be set higher than energy due to noisier chain  In case of small signals, the timestamp may not fire. In case of large signals when reading neighbours (charge sharing)  Example – channels 16 and 24 are hit and have correct timestamp (274)  Neighbours timestamps are generated by the energy comparator which is passed to the neighbours (285)

22. Trimming of Energy Threshold Before trimmingAfter trimming Channel Number Threshold Setting 118 138 128 158 148 98 108 020406080100120 Channel Number 118 138 128 158 148 98 108 020406080100120 Threshold Setting Sweep threshold across noise and histogram number of hits for each channel Normalised count Threshold x10 Amp Shaper Vbias Trim HIT

23. Linearity ADC code Test pulse amplitude code Holes Electrons

24. Non-Linearity  Non-linearity <1 %  Obtained using the on-chip test pulse circuit

25. ADC Non-linearity  INL = 2LSB  DNL = 0.6 LSB  Obtained by bypassing the front end

26. Noise Energy (keV) Input Capacitance (pF)  Noise measured at output of ADC with ADC noise removed

27. Test with mixed-alpha source  Source position in middle of detctor  Vacuum (2.5x10 -7 bar)  N-side is face up, P-side face down

28. Test with mixed-alpha source N-side P-side  No charge sharing corrections  Can identify the three energy peaks on the N-side

29. Present status of the R 3 B ASIC  R3B ASIC is under test in conjunction with the silicon sensors  Channel readout and daisy chaining are fully functional  It’s possible to trim the comparators for energy and timestamp  ADC is operational with no missing codes - INL 2LSB, DNL 0.6LSB  Linearity is good to 99%  Noise: 7keV (RMS) for short strips, 20keV for long strips at 2  s shaping  Timestamp working  Daisy chaining fully functional  Tests are continuing

30. Present status of the R 3 B Tracker  4 full outer detectors with 32 ASICs on each are complete  4 chains per side of detector, 2 are fully bonded, tested and working  Inner layer and one outer layer will be fully assembled and tested by March 2016  3 rd layer will be added at a later date

31. Thanks to the R3B tracker collaboration Contact Details Lawrence Jones IC Design Engineer, ASIC Design Group Science and Technology Facilities Council Rutherford Appleton Laboratory, Harwell Campus, Didcot OX11 0QX United Kingdom Tel +44(0)1235 446508 Fax +44(0)1235 445008 Email: lawrence.jones@stfc.ac.uk Thank you for Listening