1. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES passing parameters via registers Parameters can be passed from one module to another through registers, memory, or the stack. –Fixed values, variables, arrays of data, memory pointers. When there is a need to pass parameters among various modules, one could use CPU registers. –The programmer must clearly document the registers used for the incoming data & registers expected to have the result after the execution of the subroutine. The limited number of CPU registers a major limitation associated with this method of parameter passing.

2. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES passing parameters via memory OS and IBM BIOS frequently pass parameters via memory by defining an area of RAM and passing parameters to these locations. –There must be universal agreement as to addresses of the memory area, to ensure modules can be run on the hardware & software of various companies. –The only reason that BIOS & OS use memory area for passing parameters is because IBM & Microsoft worked closely to decide on the memory addresses. The most widely used method of passing parameters is via the stack, making parameters both register and memory independent.

3. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES passing parameters via the stack The stack is a very critical part of every program. –Playing with it can be risky. When a module is called, the stack holds the return address, where the program returns after execution. crash –If the stack contents are altered, the program can crash.

4. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES passing parameters via the stack Program 7-8, page 212, demonstrates this method of parameter passing, written with the following requirements. –The main module gets three word-sized operands from the data segment, stores them on the stack, and calls the subroutine. –The subroutine gets the operands from the stack, adds them together, holds the result in a register, and returns control to the main module. –The main module stores the result of the addition.

5. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 Step-by-step analysis of stack pointer and contents: –Assume the stack pointer has the value SP = 17FEH. –VALUE3 = 25F1H is pushed and SP = 17FC. Low byte to low address and high byte to high address. –VALUE2 = 1979H is pushed, then SP = 17FA. –VALUE1 = 3F62H is pushed, then SP = 17F8. –CALL SUBPROG6 is a FAR call, so, both CS & IP are pushed onto the stack, making SP = 17F4. See the program module listings on page 212 of your textbook.

6. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 BP BPIn the subprogram module, register BP is saved by PUSHing BP onto the stack, making SP = 17F2. BP In the subprogram, BP is used to access values in the stack.

7. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 SPBPBP SP is first copied to BP, as only BP can be used in indexing mode with the stack segment (SS) register. "MOV AX,[SP+4]“ will cause an error.

8. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 VALUE1MOV AX,[BP]+6 loads VALUE1 into AX. 17F8 –[BP]+6=17F2+6=17F8, exactly where VALUE1 is located. 17FA –BP+8=17F2+8=17FA, where VALUE2 is located. 17FCH –BP+10=17F2H+10=17FCH, where VALUE3 is located.

9. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 BP POPBPAfter all parameters are brought into the CPU by the present module & processed (in this case added), the module restores the original BP contents by POPping BP from stack. – SP = 17F4.

10. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 RET 6 RET 6 is a new instruction. – "RET n" instruction means first to POP CS:IP (IP only if the CALL was NEAR) off the top of the stack and then add n to the SP. – After popping CS and IP off the stack, the stack pointer is incremented four times, making SP = 17F8. Adding 6 to bypass the six locations of the stack where the parameters are stored makes SP = 17FEH, its original value.

11. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 7.3: PASSING PARAMETERS AMONG MODULES stack contents analysis for Program 7-8 If the program had a RET instruction, instead of the "RET 6“, every time this subprogram is executed it will cause the stack to lose six locations. –If this practice of losing some area of the stack continues, eventually the stack could be reduced to a point where the program would run out of stack and crash.

12. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 ORG ; EIGHT Dec Hex Bin 8 8 00001000 32-Bit Programming for x86

13. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 register size 386 & higher CPU register size was extended to 32 bits, with all register names changed to reflect this. –AX has become EAX, BX is now EBX, etc. 386 & higher CPUs contain registers AL, AH, AX, and EAX, with 8, 8, 16, and 32 bits, respectively.

14. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 registers FSGS CR0 CR1 CR2 CR3There are a two new segment registers: FS & GS and several control registers: CR0, CR1, CR2, CR3.

15. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 register function AXAL AHAXEAX AL AH AX EAXIn the 16-bit, register AX is accessible either as AL, AH or AX, while in the 32-bit, register EAX can be accessed only as AL, AH, AX or EAX. The same rule applies to EBX, ECX, and EDX. EAX The upper 16 bits of EAX are not accessible as a separate register.

16. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 32-bit general registers as pointers A major change from 16- to 32-bit is the ability of general registers to be used as pointers. –Such as EAX, ECX, and EDX AX, CX, and DX could not be used as pointers. Starting with the 386, these instructions are legal:

17. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 32-bit general registers as pointers EAX ECX EDX DS When EAX, ECX, or EDX are used as offset addresses, DS is the default segment register. SS ESP SS is the default segment register for ESP and EBP. CS is the default for EIP & DS for all other registers.

18. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 accessing 32-bit registers The Assembly language directive ".386" is used to access 32-bit registers of 386 and higher CPUs. –The ".386" directive means the program cannot run on 8086/286. –Additional assembler directives indicate the type of microprocessor supported by (MASM):

19. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 accessing 32-bit registers Program 8-1 demonstrates the ".386" directive, 386 32-bit instructions & simplified segment definition. –Register EAX adds/subtracts values of various size to demonstrate 32-bit programming of the x86. See the entire program listing on page 220 of your textbook.

20. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 accessing 32-bit registers In MASM, the CodeView utility allows monitoring of the execution of 16-bit and 32-bit programs. –Shown is a partial CodeView trace of Program 8-1. Register EAX adds/subtracts values of various size to demonstrate 32-bit programming of the x86.

21. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 little endian revisited x86 stores 32-bit data in memory, or loads 32-bit operands into registers with little endian convention. –Low byte to low address; high byte to high address. See the entire program listing on page 220 of your textbook. MOV RESULT,EAX An instruction such as "MOV RESULT,EAX" will store the data in this way:

22. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 little endian revisited x86 stores 32-bit data in memory, or loads 32-bit operands into registers with little endian convention. –Low byte to low address; high byte to high address.

23. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 adding 16-bit words with 32-bit registers Program 3-1B used 16-bit registers for adding several words of data. –The sum was accumulated in one register and another register was used to add up the carries. Not necessary when using 32-bit registers. See the entire program listing on page 94 of your textbook.

24. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 adding 16-bit words with 32-bit registers Review Program 3-1B, then examine Program 8-2, a 32-bit version of the same program, written for 386 and higher CPUs. See the program listing on page 222 of your textbook.

25. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 adding multiword data in 32-bit In Program 3-2, two multiword numbers were added using 16-bit registers. –Each number could be as large as 8 bytes wide. That program required a total of four iterations. See the entire program listing on page 95 of your textbook.

26. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 adding multiword data in 32-bit Using the 32-bit registers of the 386/46 requires only two iterations, as shown in Program 8-3a. See the program listing on page 223 of your textbook. However, this loop version of the program is very long &inefficient.

27. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 adding multiword data in 32-bit Due to penalties associated with instructions such as LOOP & Jcondition, in 386 and higher CPUs, it is better to use the nonloop version of this program: See the program listing on page 224 of your textbook.

28. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 combining C with Assembly Although Assembly language is the fastest language available for a given CPU, it cannot be run on different CPUs. –A portable language is needed. Today, a large portion of programs written for all computers are in the C/C++ language. –A universal programming language that it can be run on any CPU architecture with little or no modification It is simply recompiled for that CPU. –Combining C & Assembly takes advantage of C/C++'s portability and Assembly's speed.

29. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 8.1: 32-BIT PROGRAMMING IN x86 combining C with Assembly There are two ways to mix C/C++ and Assembly. –One is simply to insert the Assembly code in C programs. Commonly referred to as in-line assembly. –The second method is to make the C/C++ language call an external Assembly language procedure. The following code demonstrates how to change the cursor position to row = 10 & column = 20. –Assembly instructions are prefaced with "asm“, a reserved word. Microsoft uses the keyword "_asm".

30. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 Inserting x86 assembly code into Visual C++ programs - inlining Note that in Microsoft, not all interrupts may be supported in the latest versions of Visual C++. Each line must end in a semicolon or newline, and any comments must be in the correct form for C.

31. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 ORG ; NINE Dec Hex Bin 9 9 00001001 8088,80286 MICROPROCESSO RS AND ISA BUS

32. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR 8088 is a 40-pin microprocessor chip that can work in two modes: minimum mode and maximum mode. –Maximum mode is used to connect to 8087 coprocessor. If a coprocessor is not needed, 8088 is used in minimum mode.

33. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR data bus –Due to chip packaging limitations in the 1970s, there was great effort to use the minimum number of pins for external connections. Intel multiplexed address & data buses, using the same pins to carry two sets of information: address & data. Fig. 9-1a 8088 in minimum mode AD0AD7 –Pins 9-16 (AD0–AD7) are used for both data and addresses in 8088. AD stands for "address/data.” ALE –The ALE (address latch enable) pin signals whether the information on pins AD0–AD7 is address or data.

34. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 Fig. 9-1a 8088 in minimum mode 9.1: 8088 MICROPROCESSOR data bus ALE AD0AD7 –When 8088 sends out an address, it activates (sets high) the ALE, to indicate the information on pins AD0–AD7 is the address (A0–A7). This information must be latched, then pins AD0–AD7 are used to carry data. ALE AD0AD7 –When data is to be sent out or in, ALE is low, which indicates that AD0–AD7 will be used as data buses (D0–D7). –The process of separating address and data from pins AD0–AD7 is called demultiplexing.

35. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR address bus A0A19 –8088 has 20 address pins (A0–A19), allowing it to address a maximum of one megabyte of memory (2 20 = 1M). To demultiplex address signals, a latch must be used to grab the addresses. Fig. 9-1a 8088 in minimum mode –Widely used is the 74LS373 IC, also 74LS573, a 74LS373 variation. AD0AD7 AD0 to AD7 go to the 74LS373 latch, providing the 8-bit address A0–A7. 2839 A8–A15 come directly from the microprocessor (pins 2–8 & pin 39). 3538 –The last 4 bits of the address come from A16–A19, pin numbers 35–38.

36. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR address bus Fig. 9-2 Role of ALE in address/data demultiplexingFig. 9-3 74 LS373 D Latch The most widely used latch is the 74LS373 IC. Also used is the 74LS573, a 74LS373 variation.

37. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR address bus In any system, all addresses must be latched to provide a stable, high-drive- capability address bus. Fig. 9-5 Address,Data,and Control Buses in 8088-based System

38. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR control bus 8088 can access both memory and I/O devices for read and write operations, four operations, which need four control signals: –MEMR (memory read); MEMW (memory write). –IOR (I/O read); IOW (I/O write).

39. The x86 PC Assembly Language, Design, and Interfacing By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc. Pearson Prentice Hall - Upper Saddle River, NJ 07458 9.1: 8088 MICROPROCESSOR control bus 8088 provides three pins for control signals: –RD, WR, and IO/M. RD & WR pins are both active-low. IO/M is low for memory, high for I/O devices. Fig. 9-4 Control signal generation