1. July, 2002CMS Tracker Electronics1 APV25 wafer testing Outline Mark Raymond, Imperial College m.raymond@ic.ac.uk Wafer test procedure speed improvements feedback from hybrid tests Wafer test results update on results/problems with production lots received so far summary of current position on yield investigations

2. July, 2002CMS Tracker Electronics2 Wafer test speed improvements Wafer probe test speed now optimised at ~ 70 sec./site (~ 6 hrs/wafer) allows 2 wafers/day throughput Speed improvements achieved by: reducing any excessive averaging utilising on-chip CM correction to speed up pulse shape mapping =>pulse shapes for all channels can be acquired in two cal runs/mode only 64 chans with cal pulse 64 chans without cal pulse use average of 64 chans without Cal pulse to calculate CM correction

3. July, 2002CMS Tracker Electronics3 Feedback from hybrid tests M.Poettgens few chips showing large pedestal variation with pipeline location e.g. chip #1614 from wafer JRCSA0T why not showing up during wafer probe?

4. July, 2002CMS Tracker Electronics4 Wafer test probe data for suspect chip wafer test data for chip #1614, wafer JRCSA0T no obvious problem, pipeline scan flat (rms pipeline peds/channel low) but CM subtraction applied during pipeline scan, so any effect which mimics common mode will not be picked up (appears to be case here) test designed to be sensitive to individual pipeline cell pedestals stuck high/low

5. July, 2002CMS Tracker Electronics5 chip 1614 Histogram average channel noise for all good chips on this wafer -> single channel sticks out channel noise acquired while triggering single pipeline column => not sensitive to large pipeline CM effects solution modify wafer test to include cut on excessive CM baseline shifts during pipeline scan can apply test to all future wafer tests and can re-scan any uncut wafers – should be quick if run just this test only (~10 secs/site => 1hr/wafer) average channel noise compare suspect with other chips on same wafer JRCSA0T

6. July, 2002CMS Tracker Electronics6 APV25 wafer testing status Update on previous info presented in May CMS electronics week see http://www.hep.ph.ic.ac.uk/~dmray/pptfiles/CMS_elec_wk_2002.ppt first 10 engineering wafers (September, 2000) all diced, ~1300 KGD still available at IC 2 production wafer lots delivered January: 48 ordered, 24 + 21 = 45 delivered shortfall of 3 (rejected by manufacturer QA) processing problem – these 2 lots returned to manufacturer 3 rd full lot launched to provide remaining shortfall of 3 (25 wafers/lot) 3 wafers delivered mid Feb., remaining 22 requested and delivered in March 3 further lots launched to investigate process problems (75 wafers in total) 45 replacement wafers (from 2 lots) now received

7. July, 2002CMS Tracker Electronics7 Results from 1 st 2 production lots Lot 1 -> low yield (17 – 36 %) some good chips around periphery circular area of good chips in centre ~ even split between digital and analogue failure modes Lot 2 -> lower yield (1 – 21 %) similar circular pattern but no good chips in centre manufacturer notified via CERN (F.Faccio) investigation launched early acknowledgement of likely process problem example wafers returned and investigated a problem identified with silicide layer (gate/source/drain contact layer) these lots now replaced

8. July, 2002CMS Tracker Electronics8 Results from 3 rd production lot average yield 79% some wafers -> v. high yield others good but still show pattern 36 chips in incomplete reticles now excluded from yield calculation (previously not the case) 94% 73%

9. July, 2002CMS Tracker Electronics9 Results from replacement lots Lot A2C17000N5Lot A2C19Q00N5 33% 47% maps here for wafers with average yields failure patterns and types of failure generally similar within a particular lot some lot-to-lot differences

10. July, 2002CMS Tracker Electronics10 Results from all lots so far 82% 27% 10% 79% 33% 47% 1 st 2 “silicide” lots 3 rd lot replacements for “silicide” lots Yield histograms/lot for all wafers tested so far (average yields in green) clear lot to lot differences ~ consistent picture within lots replacement lots processed with extra checking after silicide steps – no problems observed but these lots not giving highest yield circular symmetry to failure patterns => processing problems still present and silicide defects not whole story eng. lot

11. July, 2002CMS Tracker Electronics11 Yield investigations/discussions with manufacturer brief summary of discussion during 0.25  m User Group Meeting – June 17 th problem not confined to APV wafers, 3 other HEP designs have also seen similar effects but manufacturer’s volume production not affected any common features in HEP designs? not obvious but long metal lines are possible common feature -> antenna effect (ESD sensitivity) although we are well within design rules v.large”handcrafted” layouts unusual in industry, metal layers auto-filled to higher density our metal layers less densely filled (still within design rules) -> possible under-etching? general conclusion exact cause of problem still unclear work in progress CERN test structure to investigate above theories in preparation examine test results in conjunction with layout looking for evidence to validate theories – inconclusive so far, but still ongoing

12. July, 2002CMS Tracker Electronics12 Tested chip availability present chip (KGD) availability 1300 remaining chips from engineering run 380013 wafers diced from 3 rd lot 5100in waffle packs now +3300 KGD on remaining uncut 3 rd lot wafers +6300KGD on replacement 45 wafers (assuming we keep) 16800 currently in-hand 3 wafer lots launched to replace 1 st two and investigate problems so more available

13. July, 2002CMS Tracker Electronics13 Conclusions Wafer test protocol speed improvements now allow 2 wafers /day feedback from hybrid tests will allow any loopholes to be plugged Wafer probing process problems with first two production lots – attributed to silicide problem wafers returned and replaced communication channel (via CERN) to manufacturer effective manufacturer’s response very constructive and helpful throughout 3 rd lot yield back at expected high level (average 79%) replacement lots not maintaining high yield (33% and 47%) and not silicide reasons for low yield not fully understood – more work in progress