1. 1 S PACE W IRE C OMPONENTS : S PACE W IRE CODEC IP U PDATE Chris McClements, Steve Parkes Space Technology Centre University of Dundee Kostas Marinas European Space Agency

2. 2 Contents  Introduction  System Overview  Results  Conclusion

3. Introduction  Implement serial communications protocol layer in SpaceWire  SpaceWire interface IP core developed by University of Dundee –First supplied as IP in 2003 by ESA –Widely used in over 40 ESA projects [1] Licensed directly from ESA IP cores website –Licensed from STAR-Dundee for non ESA contracts  Current version is version 2.03 –Released by Dundee in Jan 2008 –Fixes all known issues –Extra features 3 1. http://www.esa.int/TEC/Microelectronics/SEMKBWSMTWE_0.html

4. Introduction  The CODEC is implemented in technology independent RTL VHDL code –Easily implementable in a number of devices  Reference design for Actel RTAX device –Tested in STAR-Dundee Actel AX prototype board 4

5. System Overview  Wrapper of spwrlink with error recovery FIFOs 5

6. System design  System clock clocks all FFs except receive clock domain (HCLKBUF) –System clock frequency is 100 MHz generating 100 Mbit/s bit rate (TXCLK_EN) –Internal enabler for divided data rate (TXRATE)  100 MHz divides easily to 10 MHz reference (CFG_SLOWRATE_SYSCLK)  Receive clock is attached to internal RCLK network (CLKINT) –Frequency is 50 MHz for 100 MHz bit-stream  System reset is a high fanout net mapped to RCLK network (CLKINT inferred) 6

7. System Design  Transmit/Receive FIFO implemented with Actel RAM block –In the Actel RTAX parts the RAM block can be used with EDAC protection using an Actel SmartDesign core –EDAC logic implemented in FPGA fabric –FIFO control logic and pointers implemented in FPGA fabric –Scrubbing is not enabled 7

8. Results  Main features: –Error detection and recovery Actel SmartDesign cores –Single data rate link with one system clock and one receive clock –Implementation guide using Libero IDE, Synplify/Synplify Pro and Designer –Layout guidelines and static timing analysis  Performance 8 ClockRequestedAchievableDescription SYSCLK100 MHz112.18 MHz System clock frequency. RX_CLK50 MHz84.97 MHz Receive clock frequency

9. Results  Resource Usage  Global Usage 9 UsedAvailablePercentageDescription R-Cells50860488.4%Register C-Cells1095120969.1%Combinatorial R+C-Cells1603181448.8%Combined RAM2365.5%Internal RAM GlobalFanoutInferred System ClockHCLK434No ResetRCLK344No Receiver ResetRCLK75Yes Receive ClockRCLK114Yes

10. Results  Estimated power consumption 10 Power (mW)Percentage Total Power181.09- Static Power97.0153.6 % Dynamic Power84.0846.4 %

11. Conclusion  University of Dundee SpaceWire CODEC widely used –Licensed in over 40 internal ESA projects  CODEC is actively maintained by University of Dundee  RTAX reference design is capable of achieving a 100 Mbit/s data rate  Available under license from STAR- Dundee for non ESA projects 11