1. Ajay K. Verma, Philip Brisk and Paolo Ienne Processor Architecture Laboratory (LAP) & Centre for Advanced Digital Systems (CSDA) Ecole Polytechnique Fédérale de Lausanne (EPFL) csda XP 2 : A New Compact Representation for Manipulating Arithmetic Circuits

2. 2 Logic Synthesis For Arithmetic Cicruits Sum-of-Product (SoP) and Product-of-Sum (POS) Form Well-studied (e.g., Espresso), but… Arithmetic circuits are XOR-dominated Reed-Muller Form (XOR of Products) In principle, good for arithmetic circuits, but… Exponential growth in size compared to POS/SUM Parallel counter Leading Zero Anticipator (LZA) Arithmetic circuits with control logic at the periphery. Contribution: XP 2 : A Reed-Muller alternative without the exponential blowup

3. 3 Motivational Example z 0 = Maj (a 1, a 3, a 5, a 7, a 9, a 11, a 13 ) z 1 = Maj (a 0, a 1, a 2, a 3, a 4, a 5, a 6, a 7, a 8, a 9, a 10, a 11, a 12, a 13, a 14 ) 0.35 ns 705 μm 2 0.74 ns 2200 μm 2 0.75 ns 2275 μm 2 0.75 ns 2815 μm 2 Synthesis from SoP Form: 0.79 ns 16397.2 μm 2

4. 4 Outline Related work XP 2 : a new compact representation Superiority over other representations Results from abstract algebra Null spaces and their use in factorization Minimization algorithm for XP 2 representation Iterative split-merge approach Manipulation algorithms (CSE elimination) Results Conclusions and future work

5. 5 Related Work General circuits SOP/POS Form Minimisation (e.g., Espresso) [Brayton84] Factored form [Brayton82, Brayton87] Binary Decision Diagram [Lee59] Minimisation algorithm by partitioning [Yang02] Representation of XOR-dominated circuits Generalized Reed-Muller form [Sasao90] Manipulation algorithms [Verma06, Verma07] 2-SPP form [Bernasconi06] Three-level Boolean expressions [Ishikawa04]

6. 6 Sum of Products and Reed-Muller Form SP 1 = SP – SOP Form SP k – Sum of products of SP k-1 expressions The SP k representation of the XOR of n variables is exponentially large for any constant k. Theorem 2. The Reed-Muller expansion of the OR of n variables is exponentially large. The n-bit parity function is exponentially large in any SP k representation [Furst84]

7. 7 XP 2 Form XP: Generalized Reed-Muller expression PXP: Product of XP expressions XP 2 : XOR of PXP expressions XP k : XOR of PXP k-1 expressions

8. 8 Why XP 2 ? Theorem 3. If the SoP/PoS representation of a circuit has size k, then the size of the XP 2 representation is O(k) Linear growth! Reed-Muller Form grows exponentially in k f = ab + pqr + ac + xyr f = 1  (1  ab) (1  pqr) (1  ac) (1  xyr) f = (a + x) (p + y + r) (b + c) (a + r) f = (1  a x) (1  p y r) (1  b c) (1  a r) SOP XP 2 POS XP 2

9. 9 Optimizing XP 2 Expressions (acy  ady  bcef  bdef  x) XOR (ay  bef) AND (x  z) 1. Factorize ((ay  bef)(c  d)  x) (p  q) AND Not a Generalized Reed-Muller Form Expression! 2. Split (p  q) AND (c  d) (ay  bef) x (p  q) AND 3. Merge (x  z  pc  pd  qc  qd)

10. 10 CSE Elimination in XP 2 Representation find_CSE (expr E 1, expr E 2 ) { Introduce new variables λ and μ; E = λE 1  μE 2 ; minimize (E); S = set of PXP’s which have a product term of the form (λX  μY); T = {p | p(λX  μY)  S, for some X, Y}; return T; }

11. 11 CSE Elimination: An Example E 1 = (ab  cd) (p  q)  pq (c  d) E 2 = (ab  pq) (c  d)  cd (a  b) E = λE 1  μE 2 = λ(ab  cd) (p  q)  λpq (c  d)  μ(ab  pq) (c  d)  μcd (a  b) E = pq (c  d) (λ  μ)  ab (λ (p  q)  μ (c  d))  cd (λ (p  q)  μ (a  b)) CSE = {pq (c  d), ab, cd} minimization

12. 12 Experimental Setup Input circuit SOP form RM and Generalized RM form XP 2 form CSE elimination XP 2 form (CSE) Manually designed (CSE) Performance criteria: Literal Count

13. 13 Results (1 of 4) BenchmarkSOP form Generalized Reed-Muller Form XP 2 form (no CSE) XP 2 form (CSE) Manually Designed 16-bit LZD 16-bit LOD 16-bit Barrel Shifter 16-bit Adder 16-bit Comparator 15:4 Counter 15-bit Majority 12-bit CSA 16-bit LZA 220 1280 5.24 x 10 6 5.19 x 10 5 1.05 x 10 6 5.15 x 10 4 Large 332 1280 9.18 x 10 5 5.72 x 10 4 1.05 x 10 6 5.15 x 10 4 Large 1.24 x 10 12 154 896 1194 1854 246 1479 42602 3336 66 288 237 567 85 543 3136 250 64 192 89 77 63 71 152 149 Reed-Muller Form 1.81 x 10 6 602 4752 9.18 x 10 5 5.72 x 10 4 4.81 x 10 8 5.15 x 10 4 Large 1.24 x 10 12 Performance criteria: Literal Count

14. 14 Results (2 of 4) Adder SOP/GRMExponential growth as a function of bitwidth XP 2 Linear growth as a function of bitwidth

15. 15 Results (3 of 4) Barrel Shifter Not XOR-dominated XP 2 has a similar literal count as SoP/GRM

16. 16 Results (4 of 4) Reed-Muller Diminishing returns observed as k increases XP 2

17. 17 Conclusions and Future Work XP 2 XOR-based representation for arithmetic circuits Avoids exponential size complexity Logic optimization fundamentals Factorization Split Merge CSE Elimination Develop a complete logic synthesis package using XP 2

18. 18 Results from Abstract Algebra: Null Space Factorization Null space of X, N (X): All expressions F, which satisfy FX = 0 ab  N (a  b) f = (a  b) (cd  e)  (c  d) (ab  e) ab  N (a  b) cd  N (c  d) f = (a  b) (cd  ab  e)  (c  d) (ab  cd  e) f = (a  b  c  d) (ab  cd  e) f = (a  b) (cd  e)  (c  d) (ab  e) f = (a  b) (cd  ab  e)  (c  d) (ab  e) f = (a  b) (cd  ab  e)  (c  d) (ab  cd  e) f = (a  b  c  d) (ab  cd  e)

19. 19 Relative Compactness of SP k and XP k SP k (n) = set of Boolean expressions whose representation size in SP k is n XP k (n) = set of Boolean expressions whose representation size in XP k is n XP k : XOR of products of XP k-1 expressions

20. 20 Minimization of XP 2 representation Minimize (expr E) { do { Factorize (E) Split (E); Merge (E); } while (there is a reduction in size) output E; } Accepting only smaller expressions might cause sub-optimality