Presentation is loading. Please wait.

Presentation is loading. Please wait.

NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Published byGwendoline Summers Modified over 8 years ago

Similar presentations

Presentation on theme: "NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning."— Presentation transcript:

1 NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

2 311_07 NAND and NOR Gates 2

3 DeMorgan's Laws  (X ∙ Y)' = X' + Y'  (X + Y)' = X' ∙ Y' 311_073

4 Functionally Complete Set  Any function can be realized using only NAND gates 311_074

5 SOP to NAND-NAND G = WXY + YZ 5

6 311_07 MOSFETs NMOS (n-channel) PMOS (p-channel) OFF ON OFF 6

7 CMOS Inverter 311_077

8 CMOS Inverter OFF ON OFF +V (H = 1) V in Q1Q1 Q2Q2 V out 0 (L)ONOFF1 (H) OFFON0 (L) +V (H = 1) (L = 0) 8

9 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LL LH HL HH (L = 0) (H = 1) 9

10 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LH HL HH (L = 0) (H = 1) 10

11 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HL HH (L = 0) (H = 1) 11

12 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HLOFFON OFFH HH (L = 0) (H = 1) 12

13 CMOS NAND Gate 311_07 ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 F LLON OFF H LHONOFF ONH HLOFFON OFFH HH ON L (L = 0) (H = 1) 13

14 CMOS NOR Gate 311_0714

15 311_07 Noise Margin V OHmin V IHmin V OLmax V ILmax 15

16 NM H = V OHmin - V IHmin = 4.4 V - 3.15 V = 1.25 V NM L = V ILmax - V OLmax = 1.35 V - 0.1 V = 1.25 V Electrical Characteristics 311_0716

17 311_0717 Propagation Delay

18 311_0718 Propagation Delay

19 Summary  NAND and NOR Gates  DeMorgan's Laws  SOP to NAND-NAND  MOSFETs  CMOS Logic Gates Inverter, NAND, NOR  Electrical Characteristics Noise Margin Propagation Delay 311_0719

Download ppt "NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning."

Similar presentations

Digital CMOS Logic Circuits

Digital CMOS Logic Circuits
Chapter 10 Digital CMOS Logic Circuits

Chapter 10 Digital CMOS Logic Circuits
Logic Gates.

Logic Gates.
CMOS Logic Circuits.

CMOS Logic Circuits.
Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.
CMOS gates Electrical characteristics and timing TTL gates

CMOS gates Electrical characteristics and timing TTL gates
3.4 Bipolar Logic 1. Diode Logic

3.4 Bipolar Logic 1. Diode Logic
EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate.

EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate.
Digital Design: Chapters 1-5 1 Chapter 1. Introduction Digital Design - Logic Design? Analog versus Digital Once-analog now goes digital –Still pictures.

Digital Design: Chapters Chapter 1. Introduction Digital Design - Logic Design? Analog versus Digital Once-analog now goes digital –Still pictures.
Week 9b, Slide 1EECS42, Spring 2005Prof. White Week 9b OUTLINE Digital logic functions NMOS logic gates The CMOS inverter Reading Rabaey et al.: Section.

Week 9b, Slide 1EECS42, Spring 2005Prof. White Week 9b OUTLINE Digital logic functions NMOS logic gates The CMOS inverter Reading Rabaey et al.: Section.
Physical States for Bits. Black Box Representations.

Physical States for Bits. Black Box Representations.
EE365 Adv. Digital Circuit Design Clarkson University Lecture #5

EE365 Adv. Digital Circuit Design Clarkson University Lecture #5
Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates.

Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates.
CS 140L Lecture 1 Professor CK Cheng 3/31/02. CMOS Logic (3.2 – 3.6) Complementary Metal-Oxide Semiconductor.

CS 140L Lecture 1 Professor CK Cheng 3/31/02. CMOS Logic (3.2 – 3.6) Complementary Metal-Oxide Semiconductor.
3.3 CMOS Logic 1. CMOS Logic Levels NextReturn Logic levels for typical CMOS Logic circuits. Logic 1 (HIGH) Logic 0 (LOW) Undefined Logic level 5.0V 3.5V.

3.3 CMOS Logic 1. CMOS Logic Levels NextReturn Logic levels for typical CMOS Logic circuits. Logic 1 (HIGH) Logic 0 (LOW) Undefined Logic level 5.0V 3.5V.
Chapter 6 – Selected Design Topics Part 1 – The Design Space Logic and Computer Design Fundamentals.

Chapter 6 – Selected Design Topics Part 1 – The Design Space Logic and Computer Design Fundamentals.
ECE 331 – Digital System Design Multi-level Logic Circuits and NAND-NAND and NOR-NOR Circuits (Lecture #8) The slides included herein were taken from the.

ECE 331 – Digital System Design Multi-level Logic Circuits and NAND-NAND and NOR-NOR Circuits (Lecture #8) The slides included herein were taken from the.
ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.

ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.

Similar presentations

Ads by Google