1. Going to Implementation Stage
FCBGA Package Warpage
Going to Implementation Stage
Project Leader: Kirk Van Dreel, Plexus
Facilitator: Robert Smith
September 25, 2013

2. Background Package/board Warpage increasing trends
Driven by thinner package substrates and thinner die
Package/Board contacts getting smaller and closer thereby reducing ability to overcome increased Warpage.
Solder Joint Quality Impact of increasing Package and Warpage.
With advent of lead free soldering, the assembly temperatures have increased and the warpage impact has been exacerbated. 2
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3. Examples of Warpage Induced Defects
Package Substrate
Die
Board
Head-on-Pillow Open
Non –Wet Open
Stretched joint
Head on pillow
Various Solder Joint Defects can occur during SMT Reflow Soldering due to Excessive BGA component and/or Board Warpage .
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4. © HDP User Group International, Inc.
Goal
Establish a limit for dynamic package warpage that can be mitigated during board assembly without impacting solder joint quality
Need to set a baseline for today, and set what the limit is for all gaps. It will be non-package or non-PCB related
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5. Project Scope - What is IN
FCBGA Package just as its entering the SMT Reflow Oven
Die
FC BGA Package Substrate
Project Focus Area
Printed Circuit Board
Reflow Process
Temperature –Time Profile
Oven Atmosphere
Solder Paste
Rheology
Wetting
Metallurgy
Activator chemistry
Volume printed on land
Surface Finish
OSP/ENIG/ImAg/ENEPIG/ etc
Package Termination
Geometry (ball, pillar, column, etc)
Metallurgy (SAC, low Ag SAC, BiSnAg, other)
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6. Project Scope - What is OUT
Package Warpage Mitigation
Laminate Type
Stack-up
Die Thickness
Die Size
Package Warpage Measurement
Metrologies
Specifications
Die
FC BGA Package Substrate
Printed Circuit Board
Board Warpage Mitigation
Laminate Type
Stack-up
Board Warpage Measurement
Metrologies
Specifications
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7. © HDP User Group International, Inc.
Project Objectives
Identify mitigation paths for solder joint yield loss caused during the SMT reflow soldering process specifically due to the excessive warpage of package and/or boards
Evaluate these mitigation paths for their effectiveness in increasing solder joint yield despite high levels of package and/or board warpage
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8. © HDP User Group International, Inc.
Technical Discussion
Potential Mitigation Paths
Alternate solder paste and package solder ball metallurgies, i.e., low temperature solders
Alternate solder temp profiles (steep ramp, soak, spike reflow profile, for instance)
Alternate package termination geometries (instead of balls)
Optimized solder paste printing geometries 
New solder paste formulations
Tacky Fluxes, applied by dipping
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9. Project Structure Phase 1 - Test Method Development
This phase will establish a test method which will enable the team to compare and contrast the effects of the mitigation techniques.
Phase 2 - Characterization Of Mitigation Methods and Max Package Warp Specifications
This phase will leverage phase 1’s output to establish the maximum warp an optimized process can accommodate and characterize the contribution of the mitigation techniques on the process yield.
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10. Phase 1 Project Plan Project Development / Planning
Test Method Development
Process HoP Mitigation Study
Resourcing of equipment, materials, and response characteristics measurements.
Baseline Process Characterization
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11. Hot Air Rework Machine Method
Repeatability:
Controlled by a lead screw of 2 mm pitch
Accuracy:
Screw moves at a rate of 200 steps per mm
A lead screw controls the movement
of the vacuum tube both up and down
Temperature of a solder joint
Distance between bottom of package and top of board
Video camera T d
The movement of the screw can be programmed by a closed loop system with the temperature control 11
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12. Hot Air Rework Machine Method
SRT Summit 1800
Video camera
Basic Concept of Hot Air Rework Equipment and Process
Blowing heated air from the top, down on to the BGA package using a nozzle
The air heats up the package, board and solder joints
Air temperature and flow rate is controlled
Package is lifted up or down with a vacuum cup
Video Camera, if available, can record the a few solder joints on the outside row on one side of the package
The basic concept is to Lift component up or down at different temperatures to simulate dynamic warpage characteristics of package 12
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13. Solder Joint Temperature vs d vs time
Solder joints’ temperature, T
`d`, Distance between bottom of package and top of board
There were questions raised about
How accurate and repeatable was the change in `d`
How closely could a change in `d` be controlled with a change in `T` 13
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14. Shadow Moire Warpage Data
140 micron at RT
Flip Temp around 125C
40-60 microns at Reflow Temperature 14
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15. Design Considerations
Room Temperature
1.57mm
Component Substrate
325um
High CTE Epoxy Deposit
350um
Solder Ball
5mm x 5mm
100um
75um
Collapse Preform
50um
Solder Mask
1.57mm
PCBA Substrate
Solder Thieving Via
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1.22 Dia

16. Room Temperature Placed
Component Substrate
High CTE Epoxy Deposit
Solder Ball
400um
50um
in Paste
100um
Collapse Preform
Solder Mask
PCBA Substrate
Solder Thieving Via 16
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17. Just Before Liquidus 217°C Temperature
CTE Expansion:
Parameter
Unit
Value
Epoxy Thickness um
400
Epoxy CTE
10-6/°C
250
Starting Temperature °C 23
Ending Temperature
217
Z-Axis Expansion
194
Component Substrate
Solder Ball
High CTE Epoxy Deposit
519um
144um out of Paste
100um
75um
Solder Mask
PCBA Substrate
Solder Thieving Via
1.22 Dia 17
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18. Just Before Liquidus 221°C Temperature
CTE Expansion:
Parameter
Unit
Value
Width mm 5
Length
Thickness
0.075
Volume of Slug:
mm^3
1.875
PCB Thickness
1.575
Radius of Via
0.616
Component Substrate
Solder Ball
High CTE Epoxy Deposit
519um
144um out of Paste
100um
Collapse Preform
75um
Solder Mask
PCBA Substrate
Solder Thieving Via 18
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19. At Min. Peak 235°C Temperature
CTE Expansion:
Parameter
Unit
Value
Epoxy Thickness um
400
Epoxy CTE
10-6/°C
250
Starting Temperature °C 23
Ending Temperature
217
Z-Axis Expansion
194
Component Substrate
Solder Ball
High CTE Epoxy Deposit
537um
112um out of Paste
75um
Solder Mask
PCBA Substrate
Solder Thieving Via
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20. TV Layout Card is approx. 5”x6” Two part sizes Included 8 Small Parts
4 Large Parts
0.062 (1.57mm) thick
Two layer
Breakaway Parts
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21. Electrical Testing
All pads and routing is not covered with solder mask
Spacing between trace and Via is: 1 mm
Maximum Ball to Via is: 5 mm
5mm Max Between Ball and Via
1 mm Max Via and Trace
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22. Electrical Layout Considerations
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23. Reflow Test Method Factors
High
Stand-off Height Thickness
350um
700um
450um
800um
Solder Paste Thickness
100um
125um
Replications at corners: 3
Center Points: 1
Board Count: 13
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24. Team Members –to date Agilent Fujitsu Panasonic Akrometrix H3C
ParkElectro
Alcatel-Lucent
Huawei
Phillips
Arlon
Hitachi
Plexus
ASE
Hitachi-Chemical
Rockwell
Celestica
IBM
Sytech
Ciena
Indium
TTM Tech
Cisco
Intel
Viasystems
Curtiss-Wright
IST Group
Ventec
Elite Materials
Juniper
Zestron
Emerson
Kyzen
ZTE
Ericsson
Medtronic
Fiberhome
Nihon-Superior
Flextronics
Oracle
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