1.  SLIM - MimoTERA – chip design MimoTera:  AMS CUA 0.6 µm CMOS process with 14 µm epitaxial layer – (MIMOSA V),  Chip size: 17350×19607µm 2,  delivery expected ~15 th of January 2005  Chip prepared for back-thinning  Total array of 112×112 153×153µm 2 square pixels, each pixel – interdigited array of small n-well/p- epi diodes,  Respected pad positions from MIMOSA V; but larger size 85×185 µm 2 (bonding),  Four sub-arrays of 28×112 pixels read out in parallel t read/integr <100µs, no dead time – alternate integration and readout in halves of pixels, Subarray 0 Subarray 1Subarray 2Subarray 3 17.136×17.136 mm 2 digital 28 columns(30 clocks) 112 rows(114 clocks)  Combination of detection thinning and microelectronics,

2.  SLIM - MimoTERA – chip design MimoTera:  Two 9×9 interdigited arrays of n-well/p-epi diodes (5×5 µm 2 ) with two independent FE electronics,  No dead time in pixel operation – alternate reset and integration in both arrays,  In-pixel storage capacitors – choice ~0.5pF or ~5pF to cope with signal range,  Readout without CDS – kTC noise,  Signal swing ~2 V (pixel and chip output) @ 40Mpixel/s,  CVF=~250nV/e- @ 500fF; noise ~1000 e - Å 280 e - kTC (ENC) @ 500fF

3.  SLIM - MimoTERA – chip design  Pixel schematic diagram Half A Half B Switch to vddato cutconsumptionwhen lineprecharging

4.  1 chip quarter architecture  SLIM - MimoTERA – chip design 4×

5.  Column level circuit column input Half A Half B prechargingto low voltage beforeeach readout to  speed precharging to vdd voltage before each readout to  speed current source OFF horizontal lineto 3:1 MUX current source OFF  SLIM - MimoTERA – chip design

6.  Array output circuit horizontal lines (3)4.3 mm  SLIM - MimoTERA – chip design reconfigurable gainoutput amplifiergain: ×1 or ×5 3:1 MUX for 3 phasecolumn readout withincreased time for linecharging MUX buffers externalvoltage reference current biasgenerated internallyD/A Convertor