1. CS 150 – Fall 2005 – Lec 13: Computer Org I - 1 Computer Organization zComputer design as an application of digital logic design procedures zComputer = processing unit + memory system zProcessing unit = control + datapath zControl = finite state machine yInputs = machine instruction, datapath conditions yOutputs = register transfer control signals, ALU operation codes yInstruction interpretation = instruction fetch, decode, execute zDatapath = functional units + registers yFunctional units = ALU, multipliers, dividers, etc. yRegisters = program counter, shifters, storage registers

2. CS 150 – Fall 2005 – Lec 13: Computer Org I - 2 Tri-State Buffers z0, 1, Z (high impedance state) in out OE if OE then Out = In else “disconnected” + in out + OE in Basic Inverter Inverting Buffer

3. CS 150 – Fall 2005 – Lec 13: Computer Org I - 3 Tri-States vs. Mux Sel 2:1 Mux 0 1 A B A Sel 0 B Sel 1 DECDEC Sel 0101 Scales poorly for high fan-in or wide bit widths Buffer circuits simple! Scales nicely for high fan-in and wide bit widths!

4. CS 150 – Fall 2005 – Lec 13: Computer Org I - 4 Register Transfer Ld C A Sel 0 B Sel 1 DECDEC Sel 0101 C  A Sel  0; Ld  1 C  B Sel  1; Ld  1 Clk Sel Ld Clk A on Bus Ld C from Bus Bus B on Bus ?

5. CS 150 – Fall 2005 – Lec 13: Computer Org I - 5 Open Collector Concept “1” “0” + Bad! Short circuit! Low resistance path from Vdd to Gnd + Resistive Pull-up “1” “0” Wired AND Configuration: If any attached device wants wire to be “0”, it wins If all attached devices want wire to be “1”, it is Default is high Must actively drive it low

6. CS 150 – Fall 2005 – Lec 13: Computer Org I - 6 central processing unit (CPU) instruction unit – instruction fetch and interpretation FSM execution unit – functional units and registers address read/write data Processor Memory System Structure of a Computer zBlock diagram view control signals data conditions Data PathControl

7. CS 150 – Fall 2005 – Lec 13: Computer Org I - 7 LD asserted during a lo-to-hi clock transition loads new data into FFs OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK Registers zSelectively loaded – EN or LD input zOutput enable – OE input zMultiple registers – group 4 or 8 in parallel

8. CS 150 – Fall 2005 – Lec 13: Computer Org I - 8 Register Transfer zPoint-to-point connection yDedicated wires yMuxes on inputs of each register zCommon input from multiplexer yLoad enables for each register yControl signals for multiplexer zCommon bus with output enables yOutput enables and load enables for each register rt MUX rs MUX rd MUX R4 MUX rs MUX rtrdR4 BUS rsrtrdR4

9. CS 150 – Fall 2005 – Lec 13: Computer Org I - 9 RE RB RA WE WB WA D3 D2 D1 D0 Q3 Q2 Q1 Q0 Register Files zCollections of registers in one package yTwo-dimensional array of FFs yAddress used as index to a particular word ySeparate read and write addresses so can do both at same time z4 by 4 register file y16 D-FFs yOrganized as four words of four bits each yWrite-enable (load) yRead-enable (output enable)

10. CS 150 – Fall 2005 – Lec 13: Computer Org I - 10 RD WR A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO3 IO2 IO1 IO0 Memories zLarger Collections of Storage Elements yImplemented not as FFs but as much more efficient latches yHigh-density memories use 1-5 switches (transitors) per bit zStatic RAM – 1024 words each 4 bits wide yOnce written, memory holds forever (not true for denser dynamic RAM) yAddress lines to select word (10 lines for 1024 words) yRead enable xSame as output enable xOften called chip select xPermits connection of many chips into larger array yWrite enable (same as load enable) yBi-directional data lines xoutput when reading, input when writing

11. CS 150 – Fall 2005 – Lec 13: Computer Org I - 11 Instruction Sequencing zExample – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) zStep 1: Get the ADD instruction from memory into an instruction register zStep 2: Decode instruction yInstruction in IR has the code of an ADD instruction yRegister indices used to generate output enables for registers Rx and Ry yRegister index used to generate load signal for register Rz zStep 3: Execute instruction yEnable Rx and Ry output and direct to ALU ySetup ALU to perform ADD operation yDirect result to Rz so that it can be loaded into register

12. CS 150 – Fall 2005 – Lec 13: Computer Org I - 12 Instruction Types zData Manipulation yAdd, subtract yIncrement, decrement yMultiply yShift, rotate yImmediate operands zData Staging yLoad/store data to/from memory yRegister-to-register move zControl yConditional/unconditional branches in program flow ySubroutine call and return

13. CS 150 – Fall 2005 – Lec 13: Computer Org I - 13 Elements of the Control Unit (aka Instruction Unit) zStandard FSM Elements yState register yNext-state logic yOutput logic (datapath/control signaling) yMoore or synchronous Mealy machine to avoid loops unbroken by FF zPlus Additional ”Control" Registers yInstruction register (IR) yProgram counter (PC) zInputs/Outputs yOutputs control elements of data path yInputs from data path used to alter flow of program (test if zero)

14. CS 150 – Fall 2005 – Lec 13: Computer Org I - 14 zControl State Diagram (for each diagram) yReset yFetch instruction yDecode yExecute zInstructions partitioned into three classes yBranch yLoad/store yRegister-to-register zDifferent sequence through diagram for each instruction type Reset Initialize Machine Register- to-Register Branch Not Taken Branch Taken Instruction Execution Init Fetch Instr. XEQ Instr. Load/ Store Branch Incr. PC

15. CS 150 – Fall 2005 – Lec 13: Computer Org I - 15 Cin Ain Bin Sum Cout FA HA Ain Bin Sum Cin Cout HA Data Path (Hierarchy) zArithmetic circuits constructed in hierarchical and iterative fashion yEach bit in datapath is functionally identical y4-bit, 8-bit, 16-bit, 32-bit datapaths

16. CS 150 – Fall 2005 – Lec 13: Computer Org I - 16 16 AB SZN Operation 16 Data Path (ALU) zALU Block Diagram yInput: data and operation to perform yOutput: result of operation and status information

17. CS 150 – Fall 2005 – Lec 13: Computer Org I - 17 16 Z N OP 16 ACREG 16 Data Path (ALU + Registers) zAccumulator ySpecial register yOne of the inputs to ALU yOutput of ALU stored back in accumulator zOne-address instructions yOperation and address of one operand yOther operand and destination is accumulator register yAC <– AC op Mem[addr] y”Single address instructions” (AC implicit operand) zMultiple registers yPart of instruction used to choose register operands

18. CS 150 – Fall 2005 – Lec 13: Computer Org I - 18 2 bits wide 1 bit wide Data Path (Bit-slice) zBit-slice concept: iterate to build n-bit wide datapaths CO CIALU AC R0 from memory rs rt rd CO ALU AC R0 from memory rs rt rd CIALU AC R0 from memory rs rt rd

19. CS 150 – Fall 2005 – Lec 13: Computer Org I - 19 Announcements zQuizzes: Good news and bad news! zAdditional readings on-line: CLD 1ed Chapters 11, 12 zLab Checkpoints and Project yProject is a marathon, not a sprint yNot as completely specified or as straightforward as the labs: creativity, team work as well as technical skill required yDo NOT fall behind … schedule may appear to look slack, but it probably won’t be possible to catch up if you fall behind yPartner problems: Keep us informed! Don’t let it fester! yKeep up with your TA design reviews. This is really important! Take them seriously!

20. CS 150 – Fall 2005 – Lec 13: Computer Org I - 20 Announcements zAfter HW #6, length of hws will decrease … zHW #5, Q2 Re-revised specification (reposted to web): yN-S: Green Arrow 16, Yellow Arrow 8, Red 88, Green 24, Yellow 8 (NOTE: Red overlaps Green and Yellow Arrows for 24 seconds, leaving 64 seconds with the arrows off but the Red light on) yE-W: Red 56, Green 56, Yellow 8 ySuppose each column represents an 8 second interval: N-S GA GA YA RA RA RA RA RA RA RA RA RA RA RA RA R R R G G G Y R R R R R R R R E-W R R R R R R R G G G G G G G Y

21. CS 150 – Fall 2005 – Lec 13: Computer Org I - 21 Instruction Path zProgram Counter yKeeps track of program execution yAddress of next instruction to read from memory yMay have auto-increment feature or use ALU zInstruction Register yCurrent instruction yIncludes ALU operation and address of operand yAlso holds target of jump instruction yImmediate operands zRelationship to Data Path yPC may be incremented through ALU yContents of IR may also be required as input to ALU

22. CS 150 – Fall 2005 – Lec 13: Computer Org I - 22 Data Path (Memory Interface) zMemory ySeparate data and instruction memory (Harvard architecture) xTwo address busses, two data busses ySingle combined memory (Princeton architecture) xSingle address bus, single data bus zSeparate memory yALU output goes to data memory input yRegister input from data memory output yData memory address from instruction register yInstruction register from instruction memory output yInstruction memory address from program counter zSingle memory yAddress from PC or IR yMemory output to instruction and data registers yMemory input from ALU output

23. CS 150 – Fall 2005 – Lec 13: Computer Org I - 23 16 Z N OP 8 ACREG 16 load path store path Data Memory (16-bit words) 16 OP 16 PCIR 16 data addr rd wr MARControl FSM Block Diagram of Processor zRegister Transfer View of Princeton Architecture yWhich register outputs are connected to which register inputs yArrows represent data-flow, other are control signals from control FSM yMAR may be a simple multiplexer rather than separate register yMBR is split in two (REG and IR) yLoad control for each register

24. CS 150 – Fall 2005 – Lec 13: Computer Org I - 24 Control FSM 16 Z N OP 16 ACREG 16 load path store path Data Memory (16-bit words) 16 OP 16 PCIR 16 data addr rd wr Inst Memory (8-bit words) data addr Block Diagram of Processor zRegister transfer view of Harvard architecture yWhich register outputs are connected to which register inputs yArrows represent data-flow, other are control signals from control FSM yTwo MARs (PC and IR) yTwo MBRs (REG and IR) yLoad control for each register

25. CS 150 – Fall 2005 – Lec 13: Computer Org I - 25 A Simplified Processor Data-path and Memory zPrinceton architecture zRegister file zInstruction register zPC incremented through ALU zModeled after MIPS rt000 (used in 61C textbook by Patterson & Hennessy) yReally a 32 bit machine yWe’ll do a 16 bit version memory has only 255 words with a display on the last one

26. CS 150 – Fall 2005 – Lec 13: Computer Org I - 26 Processor Control zSynchronous Mealy machine zMultiple cycles per instruction

27. CS 150 – Fall 2005 – Lec 13: Computer Org I - 27 Processor Instructions zThree principal types (16 bits in each instruction) typeoprsrtrdfunct R (egister) 33334 I (mmediate) 3337 J (ump) 313 zSome of the instructions add0rsrtrd0rd = rs + rt sub0rsrtrd1rd = rs - rt and0rsrtrd2rd = rs & rt or0rsrtrd3rd = rs | rt slt0rsrtrd4rd = (rs < rt) lw1rsrtoffsetrt = mem[rs + offset] sw2rsrtoffset mem[rs + offset] = rt beq3rsrtoffset pc = pc + offset, if (rs == rt) addi4rsrtoffsetrt = rs + offset j5target addresspc = target address halt7- stop execution until reset R I J

28. CS 150 – Fall 2005 – Lec 13: Computer Org I - 28 Tracing an Instruction's Execution zInstruction: r3 = r1 + r2 R0rs=r1rt=r2rd=r3funct=0 z1. Instruction fetch yMove instruction address from PC to memory address bus yAssert memory read yMove data from memory data bus into IR yConfigure ALU to add 1 to PC yConfigure PC to store new value from ALUout z2. Instruction decode yOp-code bits of IR are input to control FSM yRest of IR bits encode the operand addresses (rs and rt) xThese go to register file

29. CS 150 – Fall 2005 – Lec 13: Computer Org I - 29 Tracing an Instruction's Execution (cont’d) zInstruction: r3 = r1 + r2 R0rs=r1rt=r2rd=r3funct=0 z3. Instruction execute ySet up ALU inputs yConfigure ALU to perform ADD operation yConfigure register file to store ALU result (rd)

30. CS 150 – Fall 2005 – Lec 13: Computer Org I - 30 Tracing an Instruction's Execution (cont’d) zStep 1

31. CS 150 – Fall 2005 – Lec 13: Computer Org I - 31 Tracing an Instruction's Execution (cont’d) zStep 2 to controller

32. CS 150 – Fall 2005 – Lec 13: Computer Org I - 32 Tracing an Instruction's Execution (cont’d) zStep 3

33. CS 150 – Fall 2005 – Lec 13: Computer Org I - 33 Register-Transfer-Level Description zControl yTransfer data btwn registers by asserting appropriate control signals zRegister transfer notation: work from register to register yInstruction fetch: mabus  PC; – move PC to memory address bus (PCmaEN, ALUmaEN) memory read; – assert memory read signal (mr, RegBmdEN) IR  memory;– load IR from memory data bus (IRld) op  add – send PC into A input, 1 into B input, add (srcA, srcB0, scrB1, op) PC  ALUout – load result of incrementing in ALU into PC (PCld, PCsel) yInstruction decode: IR to controller values of A and B read from register file (rs, rt) yInstruction execution: op  add – send regA into A input, regB into B input, add (srcA, srcB0, scrB1, op) rd  ALUout – store result of add into destination register (regWrite, wrDataSel, wrRegSel)

34. CS 150 – Fall 2005 – Lec 13: Computer Org I - 34 Register-Transfer-Level Description (cont’d) zHow many states are needed to accomplish these transfers? yData dependencies (where do values that are needed come from?) yResource conflicts (ALU, busses, etc.) zIn our case, it takes three cycles yOne for each step yAll operation within a cycle occur between rising edges of the clock zHow do we set all of the control signals to be output by the state machine? yDepends on the type of machine (Mealy, Moore, synchronous Mealy)

35. CS 150 – Fall 2005 – Lec 13: Computer Org I - 35 Review of FSM Timing step 1step 2step 3 fetch decodeexecute IR  mem[PC]; PC  PC + 1; rd  A + BA  rs B  rt to configure the data-path to do this here, when do we set the control signals?

36. CS 150 – Fall 2005 – Lec 13: Computer Org I - 36 instruction execution instruction decode LW SW ADD J reset FSM Controller for CPU (skeletal Moore FSM) zFirst pass at deriving the state diagram (Moore Machine) yThese will be further refined into sub-states instruction fetch

37. CS 150 – Fall 2005 – Lec 13: Computer Org I - 37 FSM Controller for CPU (reset and instruction fetch) zAssume Moore Machine yOutputs associated with states rather than arcs zReset state and instruction fetch sequence zOn reset (go to Fetch state) yStart fetching instructions yPC will set itself to zero mabus  PC; memory read; IR  memory data bus; PC  PC + 1; reset instruction fetch Fetch

38. CS 150 – Fall 2005 – Lec 13: Computer Org I - 38 FSM Controller for CPU (decode) zOperation Decode State yNext state branch based on operation code in instruction yRead two operands out of register file xWhat if the instruction doesn’t have two operands? instruction decode Decode branch based on value of Inst[15:13] and Inst[3:0] add

39. CS 150 – Fall 2005 – Lec 13: Computer Org I - 39 FSM Controller for CPU (Instruction Execution) zFor add instruction yConfigure ALU and store result in register rd  A + B yOther instructions may require multiple cycles instruction execution add

40. CS 150 – Fall 2005 – Lec 13: Computer Org I - 40 FSM Controller for CPU (Add Instruction) zPutting it all together and closing the loop ythe famous instruction fetch decode execute cycle reset instruction fetch Fetchinstruction decode Decode add instruction execution add

41. CS 150 – Fall 2005 – Lec 13: Computer Org I - 41 FSM Controller for CPU zNow we need to repeat this for all the instructions of our processor yFetch and decode states stay the same yDifferent execution states for each instruction xSome may require multiple states if available register transfer paths require sequencing of steps