1. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 1 - LHC Upgrade Workshop CERN, April 2008 M.Trimpl, Fermilab SPI – Serial Powering Interface - SPI Motivation, powering schemes - Chip architecture and features - Assembly, heat dissipation issues - Interface controller, ADC, shunt, OverPower Protection - Summary and Outlook Joint effort with RAL (M.Weber,G.Villani), UPenn (M.Newcomer, N.Dressnandt)

2. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 2 - Serial Powering Schemes - Motivation 1) External shunt regulator + transistor Good approach, but implies a high current shunt -> limited experience in HEP-IC community SP device enables to operate non SP-ROIC in SP mode 2) Internal shunt regulator + transistor in each ROIC Disadvantage: many power supplies in parallel Matching issue can cause hot spots and potentially kill chips 3) External SR + parallel shunt transistor in ROIC feedback however more challenging and depends on implementation choice of architecture not obvious, detailed studies anticipated by RAL/LBNL (M.Weber, C.Haber) SPI chip should cover scheme (1) and (3) scheme (2) can be realized by any ROIC standalone

3. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 3 - shunt creates Vchip (scheme1), distr. shunt (scheme3) communication via multi drop bus (each SPI chip has 5bit address) spare AC coupled interfaces (comports) ADCs to monitor shunt and LR current 2x LinReg: separate analog / digital supply to hook up some chips (1-3) for tests Not proposed as a scaleable solution for a whole module (linregs should be in the ROIC, as e.g. in the ABCn) on-chip OverPower protection (avoids detector hot spots) radtol. design techniques, TSMC 025MM process SPI – Architecture Overview versatile SP chip - list of basic features:

4. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 4 - Power on Reset: all Registers set to a default condition when chip power comes up (current alarm default: ‘hard wired’ to ‘false’!) Shunt sets operation voltage: ~1.5 … ~2.5V (4bit to select, default: 1.5V), current capability: 1Amp min. AC coupled interface: 8 comports, bi-directional (input/output) - tbd rate: ~50MHz-200Mhz (depending on vdd) (based on Nova design from T.Zimmerman, Implementation: N.Dressnandt) Distr. Shunt: class AB stage with dual output (redundancy) – M.Newcomer Linear regulator: LDO regulator (folded cascode OTA and output stage) Vout: ~1.2 – ~2.5V (VDO ~200-300mA for 500mA), with 1uF ESR for stability 4bit to select voltage -> ~100mV steps (somehow) more details Distributed Shunt Concept AC coupled multidrop configuration:

5. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 5 - Advantages of bump bonds (for the SPI chip) better routing flexibility (esp. on chip, kind of 3d approach) more robust and shorter (100  m vs 5mm) connection as wire bonds: reliable connection is essential in SP scheme more robust in magnetic field (5T) while ramping high currents (2A) better scale ability (if higher currents are needed) chip backside is still fully accessible for cooling PCB chip optional backside cooling (air / heat sink)

6. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 6 - 325um 250um Chip size: 5.7 x 2.6 mm 2, ~150 bumps solder chip to PCB Bump- / Floorplan one (out of 8) comportsLinreg Vout (2x) Fanout (finger) for shunt

7. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 7 - TSMC is placing the solder bumps! various vendors are able to do assembly Very first alignment tests done using glass samples and adhesive: <10  m misalign. on 8mm [J.Krider, FNAL] Bonding (Assembly) Alignment marker: 200  m squares with 12  m spacing -> sufficient for SPI bumping (wrt alignment) Next step: Daisy chains modules from IZM (300  m pitch) to test solder assembly (2mm targets shown) Suess MA8 FC-Bonder at Fermi -> in house assembly 1cm 2 alignment mask (glass):

8. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 8 - 'shunt' ADC – principle of operation new proposal : a) probing shunt current similar to a current mirror! b) current-mode ADC Different ADC-implementations possible: - successive: smart (future iterations?) - flash: simple and fast

9. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 9 - 590  m 320  m ADC – Implementation present ADC-implementation: 6bit flash with tunable LSB (4bit) 16mA: full 1A dyn. Range 1 mA: 64mA dyn. Range (probing low current) 4bits to tune the delay (alarm)

10. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 10 - ADC (full) simulation only post layout simulation missing…

11. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 11 - Linreg

12. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 12 - stability phase margin ~70 deg ( worst case: 50deg, depending on Vdd and the comp caps)

13. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 13 - voltage steps @500mA load (range: 2.3 to 1.2V)

14. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 14 - output impedance output impedance: 20kHz9m Ohm 200kHz90m Ohm 2MHz780m Ohm 20Mhz1.2 Ohm (fits to the transient result)

15. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 15 - Principle of OverPower Protection 1. OverPower is NOT OverCurrent -> current should stay the same in SP scheme! 2. Power reduction by collapsing the chip voltage 3. Goal: reduce Vchip to minimum e.g. 50mV and 4A -> P ~ 200mW - in the order of nominal operation - comparable to ROIC on module -> no hot spot! Sounds crazy, but serial powering is already! Procedure: 1. ADC reports current alarm or power down command 2. Amplifier decoupled, Vshunt connected to Vbuffer (2.5V) -> forces shunt-mos in lin.region & reduces Vchip (Ron*I) -> whole chip collapses, only shunt maintains operatio 3. let's see how far (long) we can go using a simple buffer cap - very attractive for pulsed powered schemes - for permanent power down basically leakage effects need to be compensated (short ramp up to recharge)

16. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 16 - 50m  2.7m  Power shunt (DC) postlayout to include parasitics Note, 4 finger pairs assumed (old), newer design uses 3 finger but more bumps -> similar or better performance expected

17. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 17 - 50m  2.7m  Power shunt (DC) Spice-Simulation with 1A per finger pair @120C, Vshunt=1.5V (worst case overpower-protection scenario) -> average current per bump: ~100mA, max rating 240mA Voltage drops: 20mV from pure MOS model (Ron) 5mV from on chip routing (bump bond approach helps here a lot!) 25mV from ‘Off chip’ routing: Rbump, Rtrace Vdrop,total ~ 50mV Conclusion: - Take these numbers with a grain of salt! - However, they give good indication for feasibility e.g. a different routing topology which didn’t look too bad at first resulted in ~500mV drop - For 1A total current we should be on a safe side (note, this simulation uses 1A per finger (4 of them!)

18. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 18 - Reusable verilog code from J.Hoff, FNAL [1100111 CCCCC RRRRR III DDDDDDDD 0000] 32 bit command word (7bit header, 4 bit trailer): C: 5bit Chip Adr. (30 chips on module) R: Register Adr. (~20 regs) D: 8bit register word III: - Reset Register - Set Register - Default (hard coded) - Read ADC / Write Register interface controller 800um 1200um then auto place and route using CERN radtol lib

19. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 19 - Status S,L : 100% in progress S: ~100% L: 0 S: 100% L: ~ 90% S: 100% L: ~80% S: ~100% L: ~60% outside of that: LVDS and CMOS pads, comports, distr.shunt

20. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 20 - SPI – Serial Powering Interface: generic chip to explore SP schemes High current shunt (1A + ), distributed shunt, AC coupled comports, Linregs, Monitoring ADCs, over power protection We believe that for 'single shunt on module' approach, FC solder is the way to go -> explore chip on board assembly Submission of Demonstrator (SPI 0.01*) anticipated in the next 6 weeks -> design review 09. Mai Order in process to get 120 chips (40 with solder bumps, 80 w/o) * Yes, we do think that there will be six more iterations ;-) Summary / Outlook

21. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 21 - Backup Slides

22. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 22 - Serial powering: present and future abc-n module approach (goal 2008): [C.Haber, LBNL] 2x10 ROIC on a module 20 modules in a row ATLAS SCT Setup at RAL (similar setup at LBNL)‏ uses discrete components explore new features: Current monitoring and Overcurrent protection‏ Starting point of development: Replace this PCB by radtol ASIC

23. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 23 - Output impedance

24. LHC Power Workshop, CERN, 07.04.2008 Marcel Trimpl, Fermilab - 24 - Some numbers… - Lorentz Force: B=5T, L(bump)=100um, Imax = 2A / 20 = 100mA Fmax = q v B = L I B = 50uN - Thermal conductivity: Si:150, Sn: 67, Pb: 35, Au:320, Ag: 430 [W per m and K]