1. 1 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Revision Dr. Paul D. Franzon Outline 1. Revision points 2. Digital system timing

2. 2 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Revision Points I do expect you to be very familiar with at least the following concepts: l Different combinational logic structures, including gates, adders, multipliexors, coders, decoders, etc. l Combinational logic optimization l Flip-flops and latches, and their operation. l Timing diagrams. How to produce one. l Finite State Machines – purpose, operation, types, state vector encoding l Counters – basic operation l MOST IMPORTANTLY, I expect you to be able to design a logic function to a specification (like Q7 with relative ease) If any of these topics are NOT familiar to you, I suggest reviewing your undergraduate logic course or logic course text. If that is not available to you, there are many suitable texts in the library. Authors include Katz, Wakerley, Mano, but there are many other.s

3. 3 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes General Principles of Digital System Design Most Digital Systems are Synchronous l I.e. All signals are derived off a single Master Clock fed to all registers l In most logic implementation families, events are synchronized using edge- triggered flip-flops u e.g. positive-edge triggered D- or Data- flip-flop l Groups of flip-flops are referred to as registers D clock Q In[0] In[1] In[2] In[3] Out[0] Out[1] Out[2] Out[3] clock After a 0->1 transistion at clock Q takes the value of D that was present just before that transition.

4. 4 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Timing Diagram The core tool for analyzing synchronous digital designs is a timing diagram. D clock Q D Q Don’t know (Don’t care) “x” Glitches at input do not appear at output. F/F only samples ‘D’ at positive clock edge.

5. 5 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Multiple Logic Stages Generate Timing Diagram In[0] In[1] In[2] In[3] clock Out[0] Out[1] Out[2] Out[3] Clock In Out F 1 A 5 x F2AA

6. 6 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Animation Track the logic… In[0] In[1] In[2] In[3] clock Out[0] Out[1] Out[2] Out[3] Clock In Out 5 1 0 1 0 0 1 0 1 A 0 1 0 1

7. 7 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Logic With Feedback Generate Timing Diagram In[0] In[1] In[2] In[3] clock Out[0] Out[1] Out[2] Clock In Out A 1 B 5 3 4013 Q. If we don’t know the initial value of “Out” can we answer this question? No! Later, we’ll discuss how to use a global reset to initlialize registers.

8. 8 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Snapshot In[0] In[1] In[2] In[3] clock Out[0] Clock In Out A 1 B 5 Out[1] Out[2] 3 0 1 0 1 1 0 0 1 0 4

9. 9 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes What is Wrong Here? Combinational Logic Feedback does not work in synchronous design l Must Feedback through register l What happens if the logic gets into the state shown? In[0] In[1] In[2] In[3] clock Out[0] Out[1] Out[2] 1 0 1 1 1 Logic point * will oscillate 101010… Given that logic delays vary with temperature and from chip to chip, what value will be valid at D input to Out[2]? Don’t know!

10. 10 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes …Digital System Design Digital sub-systems are built as collections of registers and combinational logic l Registers store data from the end of one clock period to be available at the start of the next clock period l Combinational logic can not store data u It only operates on it during each clock period In1[3:0] In2[3:0] nextA[3:0] + 2 A[3:0] nextB[3:0] B[3:0] clock selB

11. 11 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes What is wrong here? DQ Ck cl DQ Ck cl …logic… 2 clock periods of delay DQ Ck cl clock reset Any logic block only operates on data coming out of the LH Flip-flop after start of clock period to present to input of RH flip-flop before end of clock period. Can not operate over 2 periods. Does NOT have internal storage.

12. 12 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Sample Design Problem Accumulator: l Design an 8-bit adder accumulator with the following properties: l While ‘accumulate’ is high, adds the input, ‘in1’ to the current accumulated total and add the result to the contents of register with output ‘accum_out’. u use absolute (not 2’s complement) numbers l When ‘clear’ is high (‘accumulate’ will be low) clear the contents of the register with output ‘accum_out’ l The ‘overflow’ flag is high is the adder overflows Hint: 8-bit adder produces a 9-bit result: {carry_out, sum} = A+B;

13. 13 © Dr. Paul D. Franzon, 2009, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Sketch Design 1. Determine and name registers. accum_out 2. Determine combinational logic + overflow accum_in in1 0 Clear accumulate