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F = ABD + ABD + ABD + BCD _ __ _ _ Another thing about Karnaugh Maps… 1 A D C 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1110 1001 0000 1110 B The two blue.

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Presentation on theme: "F = ABD + ABD + ABD + BCD _ __ _ _ Another thing about Karnaugh Maps… 1 A D C 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1110 1001 0000 1110 B The two blue."— Presentation transcript:

1 F = ABD + ABD + ABD + BCD _ __ _ _ Another thing about Karnaugh Maps… 1 A D C 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1110 1001 0000 1110 B The two blue lines are logically adjacent to each other. So are the two red lines. So, when grouping the 1s…

2 F = ABD + ABD + ABD + BCD _ __ _ _ Let’s check our work… 2 A D C 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1110 1001 0000 1110 B 11111111000000001111111100000000 11110000111100001111000011110000 11001100110011001100110011001100 10101010101010101010101010101010 01010000000000000101000000000000 00000000010100000000000001010000 00001010000000000000101000000000 10000000100000001000000010000000 11011010110100001101101011010000 00000000111111110000000011111111 00001111000011110000111100001111 00110011001100110011001100110011 01010101010101010101010101010101 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ABCDABCDFABCDABCDF ABD BCD ____ _ _ _ _ _ _ _ _

3 Logic Gates 3

4 4

5 Example 10.14 5 Using AND, OR, and INVERTER gates, implement F = AB + CD + BCD. _ Start with the 4 inputs A, B, C, and D. Use an inverter to create D. AND together the necessary terms to obtain each of the three terms of F, then OR the three terms together. _

6 A little practical insight… 6 NAND and NOR gates are preferred to AND and OR gates for several reasons (simpler circuitry, faster operation, etc.). Can you implement the last example using only NAND and NOR gates? XY ___ XY1 NAND 011 110 ___

7 A little practical insight… 7 NAND and NOR gates are preferred to AND and OR gates for several reasons (simpler circuitry, faster operation, etc.). Can you implement the last example using only NAND and NOR gates? 7400-1 7400-2 7400-3 7400-4 7400-5 7400-6 7420-1 7400-7 741G27 2 – 7400Quad 2-input NAND 1 – 7420Dual 4-input NAND 1 – 741G27Single 3-input NOR

8 A little practical insight… 8 2-input NAND TTL circuit (Transistor-Transistor Logic)

9 A little practical insight… 9 Logic FamilySwitchingPower perYear (Technology)Speed (MHz)Gate (mW)Introduced RTL (Resistor- 4 101963 Transistor Logic) DTL (Diode- varies 101962 Transistor Logic) CMOS up to 125 0.51970-1985 (Complementary Metal-Oxide Semiconductor) TTL (Transistor- typically 100 1-101964-2004 Transistor Logic) (up to 1.125 GHz) ECL (Emitter- 150-500 25-601968-1981 Coupled Logic) Apollo Guidance Computer


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